Patents by Inventor Scott T. Bingham

Scott T. Bingham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for performing a bus lock and translation lookaside buffer invalidation
    Patent number: 9916243
    Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 13, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Walker, Paul J. Moyer, Richard M. Born, Eric Morton, David Christie, Marius Evers, Scott T. Bingham
  • METHOD AND APPARATUS FOR PERFORMING A BUS LOCK AND TRANSLATION LOOKASIDE BUFFER INVALIDATION
    Publication number: 20150120976
    Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 30, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: William L. Walker, Paul J. Moyer, Richard M. Born, Eric Morton, David Christie, Marius Evers, Scott T. Bingham
  • ORDERING AND BANDWIDTH IMPROVEMENTS FOR LOAD AND STORE UNIT AND DATA CACHE
    Publication number: 20150121046
    Abstract: The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes a load order queue for cacheable operations that ordered for a particular address.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Thomas Kunjan, Scott T. Bingham, Marius Evers, James D. Williams