Abstract: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Abstract: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Abstract: A Communication Assets Survey and Mapping Tool. The method includes collecting and storing agency, communication asset and interoperability data in a database, receiving a request for a display of agency, communication asset and interoperability of a geographic area, retrieving data regarding agency, communication asset and interoperability information from the database, determining interoperability between agencies based on their communication assets data and displaying interoperability information. Features include prioritizing interoperability solutions (a need vs ability analysis), data entry graphical user interface, data export, and community forum.

Abstract: A Communication Assets Survey and Mapping Tool. The method includes collecting and storing agency, communication asset and interoperability data in a database, receiving a request for a display of agency, communication asset and interoperability of a geographic area, retrieving data regarding agency, communication asset and interoperability information from the database, determining interoperability between agencies based on their communication assets data and displaying interoperability information. Features include prioritizing interoperability solutions (a need vs ability analysis), data entry graphical user interface, data export, and community forum.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Abstract: A Communication Assets Survey and Mapping Tool. The method includes collecting and storing agency, communication asset and interoperability data in a database, receiving a request for a display of agency, communication asset and interoperability of a geographic area, retrieving data regarding agency, communication asset and interoperability information from the database, determining interoperability between agencies based on their communication assets data and displaying interoperability information. Features include prioritizing interoperability solutions (a need vs ability analysis), data entry graphical user interface, data export, and community forum.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Abstract: A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.

Abstract: A differential register slave structure is presented. In one embodiment, a differential register includes a storage node (218, 318). The storage node (218, 318) stores and holds the differential values generated by the differential register. In one embodiment of the present invention, on power-up, when the state of various clocks (i.e., master, slave) in the differential register may be indeterminate, the storage node (218, 318) will discharge the differential values and the differential register will produce a differential output.

Abstract: A method for minimizing clock skew in a balanced tree when interfacing to an unbalanced load is presented. Unused portions of the balanced tree are replaced by a loading equivalent circuit to create a physically balanced load. In the preferred embodiment, the loading equivalent circuit is implemented with a single-pole resistor-capacitor circuit that has been modeled to match the RC characteristics of the replaced branch of the tree.

Abstract: A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.

Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.

Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.

Abstract: A method for minimizing clock skew in a balanced tree when interfacing to an unbalanced load is presented. Unused portions of the balanced tree are replaced by a loading equivalent circuit to create a physically balanced load. In the preferred embodiment, the loading equivalent circuit is implemented with a single-pole resistor-capacitor circuit that has been modeled to match the RC characteristics of the replaced branch of the tree.

Abstract: A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.

Abstract: A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.

Abstract: A circuit arrangement according to the invention is intended to be used in a PIR motion-activated lighting fixture of the type that includes a triac for energizing the light from the AC power mains and a triac firing circuit for firing the triac in response to motion. To provide the accent lighting level and to control the magnitude of that level, the circuitry includes a window comparator, in which the thresholds are set to defining a dimming window, and a filter circuit responsive to the AC power line and providing an input signal to the window comparator. The filter circuit includes a circuit arrangement for shifting the phase of the input signal with respect to the AC power line signal and for contemporaneously scaling the amplitude of the input signal with respect to the AC power line signal such that the peak amplitude of the input signal diminishes as the phase shift of the input signal increases.

Abstract: A digital interpolating system transmits a digital output value that is within a linear range defined by a minimum value and a maximum value input into the system. Another input value, a control value, indicates which value within the linear range should be output by the system as an interpolated output value. The system utilizes a simple hardware design to efficiently implement an approximation of an equation of a line defined by the minimum and maximum values input into the system. The hardware design includes a plurality of switching devices, such as multiplexers or switches, and a plurality of adders to implement the approximation of the equation. By approximating the equation, the system is capable of providing the minimum and the maximum value input into the system as the interpolated output value when the control value is at a minimum and a maximum, respectively.

Abstract: Method and apparatus for treating confined material such as buried waste or areas of contaminated earth by injecting a plurality of high velocity jets of treating fluid into the material over a limited depth in multiple direction from each of a plurality of injection holes. The high velocity jets remain stationary, but the arrangement of the jets emanating from an injection hole in multiple directions produces a result similar to a rotating jet but with increased penetrating force. The jets are operated sequentially over the limited depth of each injection hole to treat a layer of the material and are then moved and again operated sequentially over another limited depth of each injection hole to provide treatment of the material by layers. This allows effective treatment of material surrounding each injection hole without substantial interference from treating fluid flowing through the material from a previously treated hole.

Abstract: An infrared motion detection device for detecting the presence of a target object including special circuitry for reducing false alarms. In particular, coupling circuitry is interposed between signal processing circuitry and comparator circuitry, which serves to match the baseline level of the signal from the signal processing circuitry with the baseline level of a threshold or thresholds defined by the comparator circuitry. The coupling circuitry may be implemented in a particularly simple manner, which reduces the manufacturing cost of the circuitry and the device.