Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately moveable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another.

Abstract: A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of design partitions of an integrated circuit system to create a clock system that reduces peak power consumption across the system. The method used to create the design structure includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals.

Abstract: A method that utilizes connectivity and/or timing information among a plurality of design partitions of an circuit system to create a clock system that reduces peak power consumption across the system. The method includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals.

Abstract: A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately moveable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately movable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another.

Abstract: A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately movable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

Abstract: A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.