Abstract: Accordingly, a digital logic circuit in the form of a finite state machine (FSM) is implemented in a semiconductor structure such as complementary metal oxide silicon (CMOS) with reduced power dissipation by determining transition probabilities for transitions between states in the FSM, producing a constraint matrix to identify constraints to producing a minimum area implementation consistent with minimum power dissipation, constructing one or more state chains having transitions with highest probability and implementing each of these state chains in order of probability to achieve the implementation of the FSM having minimum power dissipation.