Abstract: A system for hierarchical variable code rate error correction coding may include at least one circuit that is configured to identify a row of a hierarchical portion of a generator matrix that corresponds to a determined code rate, determine a number of information bits to apply to the hierarchical portion based at least on the identified row, and apply the determined number of information bits to the identified row. The circuit may be further configured to apply an output of the identified row to a subsequent row of the hierarchical portion, when the hierarchical portion includes a subsequent row, and apply an output of a last row of the hierarchical portion to a base portion of the generator matrix. The circuit may be further configured to provide a codeword output by the base portion of the generator matrix.

Abstract: A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.

Abstract: A system for hierarchical variable code rate error correction coding may include at least one circuit that is configured to identify a row of a hierarchical portion of a generator matrix that corresponds to a determined code rate, determine a number of information bits to apply to the hierarchical portion based at least on the identified row, and apply the determined number of information bits to the identified row. The circuit may be further configured to apply an output of the identified row to a subsequent row of the hierarchical portion, when the hierarchical portion includes a subsequent row, and apply an output of a last row of the hierarchical portion to a base portion of the generator matrix. The circuit may be further configured to provide a codeword output by the base portion of the generator matrix.

Abstract: A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.