Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Abstract: A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line and the victim line are an aggressor/victim line pair from multiple aggressor/victim line pairs in a circuit. Determination of the noise level is conducted during a predetermined window of time during which a signal is being transmitted along the aggressor line. Each of the multiple aggressor/victim line pairs are ranked according to a level of noise being imposed by each aggressor line on each victim line. The spacing between a highest ranked aggressor/victim line pair is then expanded.