Abstract: Mating faces of a microchannel plate (MCP) (50) and a multi-layer ceramic body (80) unit are deposited with a thin film having protuberances (84) using a suitable metal selected for optimum diffusion at a desired temperatures and pressure. The metallized MCP (50) and multi-layer ceramic body (80) unit are then aligned and placed in a bonding fixture (F) that provides the necessary force applied to the components to initiate a diffusion bond at a desired elevated temperature. The bonding fixture (F) is then placed in a vacuum heat chamber (V) to accelerate the diffusion bonding process between the MCP (50) and the multi-layer ceramic body unit (80).

Abstract: A faceplate (F) for an image intensifier tube (10) for reducing veiling glare begins as a blank (36) of optical material of a desired glass composition having a shape that conforms substantially to a configuration of the faceplate (F) to be produced. An extraneous removable aperture step portion (54) is formed on the glass blank (36). The glass blank is blackened (41) and the aperture step portion (54) is removed creating a desired transmissive aperture (34) through the glass blank (36).

Abstract: Mating faces of a microchannel plate (MCP) (50) and a multi-layer ceramic body (80) unit are deposited with a thin film having protuberances (84) using a suitable metal selected for optimum diffusion at a desired temperatures and pressure. The metallized MCP (50) and multi-layer ceramic body (80) unit are then aligned and placed in a bonding fixture (F) that provides the necessary force applied to the components to initiate a diffusion bond at a desired elevated temperature. The bonding fixture (F) is then placed in a vacuum heat chamber (V) to accelerate the diffusion bonding process between the MCP (50) and the multi-layer ceramic body unit (80).

Abstract: A microchannel plate (MCP) (50) and a dielectric insulator (80) are deposited with a thin film (54, 84) using a suitable metal selected for optimum diffusion. The metallized MCP (50) and dielectric insulator (80) are then aligned and placed in a bonding fixture (36) that provides the necessary force applied to the components to initiate a diffusion bond. The bonding fixture (36) is then placed in a vacuum heat chamber to accelerate the diffusion bonding process between the MCP (50) and the dielectric insulator (80).

Abstract: Methods and apparatus to detect terminal open circuits and short circuits to ground in inductive head write drivers are presented. A exemplary method is provided for detecting a short-circuit condition at at least one of a pair of write head terminals of a write driver, the write driver producing a write current that, when passed through a inductive head assembly coupled to the pair of write head terminals, polarizes the inductive head according to a direction of the write current. The method includes the step of generating a first current that is proportional to at least a portion of the write current that flows in a first direction into a first write head terminal of the write driver. A second current is generated that is proportional to at least a portion of the write current that flows in a second direction, opposite the first direction, into a second write head terminal of the write driver.

Abstract: Methods and apparatus to detect terminal open circuits and short circuits to ground in inductive head write drivers are presented. A exemplary method is provided for detecting a short-circuit condition at at least one of a pair of write head terminals of a write driver, the write driver producing a write current that, when passed through a inductive head assembly coupled to the pair of write head terminals, polarizes the inductive head according to a direction of the write current. The method includes the step of generating a first current that is proportional to at least a portion of the write current that flows in a first direction into a first write head terminal of the write driver. A second current is generated that is proportional to at least a portion of the write current that flows in a second direction, opposite the first direction, into a second write head terminal of the write driver.

Abstract: Shorts are detected in terminals fed current by a driver connected to the terminals. To detect terminal-to-ground shorts, at least one virtual driver is connected to the driver for processing an output of the driver, and a detector detects if a short has occurred, based on an output of the virtual driver, by detecting when an output of the virtual driver exceeds a first threshold. If the detector detects that the output of the virtual driver has exceeded the first threshold, this indicates a terminal-to-ground short. To detect terminal-to-terminals shorts, a detector detects when an output of the driver drops below a second threshold. If the detector detects that the output of the driver has dropped below the second threshold, this indicates a terminal-to-terminal short. Shorts may be detected in terminals in one or more write heads. The driver, virtual driver, and detector may be included in a preamplifier.

Abstract: A sigma-delta analog-to-digital (A/D) converter has an analog modulator, and an adjustable reference voltage circuit that provides a reference voltage to the analog modulator along a feedback path during A/D conversion. The reference voltage circuit includes a reference voltage generator that provides a plurality of positive and negative polarity signals to a gain multiplexer. The gain multiplexer selectively supplies a pair of positive and negative polarity signals to the analog modulator based on a select signal produced by a gain register and a microprocessor interface bus that together allow adjustment of the range of operation and performance of the sigma-delta A/D converter. This adjustment is made based on a particular application in which the converter is implemented; as the relative input power of an input signal changes, the sigma-delta A/D converter as dynamically adjusted, realizes higher performance.

Abstract: A circuit and method for compensating for the output phase delay of an external clock signal utilizes a phase-locked loop that includes an output port of an integrated circuit device. In the phase-locked loop, a phase detecting circuit compares the external clock signal with an output signal from the output port, producing a phase error signal. The phase error signal is applied to a skew compensator to generate an internal clock signal. The internal clock signal is fed back through the output port to the phase detecting circuit. Clock jitter is reduced by reducing the gain of the skew compensator after a phase lock condition occurs in the compensation circuit.