Patents by Inventor Scott UEDA

Scott UEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240052493
    Abstract: This invention allows for the deposition of aluminum nitride buffer layers and templating films that greatly enhance the quality of additional aluminum nitride deposited by alternate deposit ion techniques and reduce the overall thickness of needed buffer layers. Furthermore, these films can be deposited at substrate temperatures of 400° C. and 580° C. which is considerably lower than other techniques, such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
    Type: Application
    Filed: May 2, 2023
    Publication date: February 15, 2024
    Inventors: Aaron McLeod, Scott Ueda, Andrew Kummel
  • Publication number: 20210249331
    Abstract: Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 12, 2021
    Inventors: Scott Ueda, Aaron McLeod, Andrew Kummel, Mike Burkland, Eduardo M. Chumbes, Thomas E. Kazior, Eric Pop, Michelle Chen, Chris Perez, Mark Rodwell
  • Patent number: 10840350
    Abstract: The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 17, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Zi-Wei Fang, Hong-Fa Luan, Wilman Tsai, Kasra Sardashti, Maximillian Clemons, Scott Ueda, Mahmut Kavrik, Iljo Kwak, Andrew Kummel, Hsiang-Pi Chang
  • Publication number: 20180122916
    Abstract: The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 3, 2018
    Inventors: Zi-Wei FANG, Hong-Fa LUAN, Wilman TSAI, Kasra SARDASHTI, Maximillian CLEMONS, Scott UEDA, Mahmut KAVRIK, Iljo KWAK, Andrew KUMMEL, Hsiang-Pi CHANG