Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.

Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.