Abstract: A semiconductor chip is described having a plurality of processing cores. The semiconductor chip also includes a plurality of test controllers. Each test controller is associated with a different one of the processing cores. The semiconductor chip also includes a test port having a first serial input and a first serial output. The first serial input is to receive serial test input data provided to the semiconductor chip. The first serial output is to provide serial output data provided by the semiconductor chip. The semiconductor chip further includes switch circuitry coupled to the test port and the plurality of test controllers. The switch circuitry is to route the serial test input data to one of the plurality of test controllers and to route the serial output data from one of the plurality of test controllers to the first serial output. The semiconductor chip further includes a configuration register coupled to the switch circuitry to establish the switch circuitry's routing configuration.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: A method, apparatus, and system are provided for testing multi-core processors. The testing includes a test control mechanism and a multi-core processor including a set of cores with at least one core having a test access port controller (TAPC), distributed data, and a set of distributed control registers. The multi-core processor and the test control mechanism further having a configuration to provide testing the multi-core processor. The test control mechanism is modified to simultaneously test multiple cores.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.

Abstract: A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.