Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: A system for managing the flow of real time data streams into a data system cache memory is disclosed. The data system includes a central processing unit or micro controller, with a cache memory, which operates at a relatively fast operating speed, near that of the central processing unit. An interrupt controller is provided as well as a quantization timer that disables the interrupts to the CPU during an execution quantization (EQ) period, and allows the interrupts to pass at an EQ boundary. In operation, the quantization timer controls interrupts to occur only when cache load actions are at a specific quantized time, thus ensuring that a given task in the cache will execute or load for a given quantized length of time, and therefore, the possibility of loading a cache randomly only to execute a few instructions is eliminated.