Patents by Inventor Scott Warrick
Scott Warrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210082811Abstract: A method for fabricating an integrated circuit upon a substrate may include forming a passive electrical component in a non-final layer of the integrated circuit and forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner such that an imaginary line perpendicular to and from a surface of the substrate intersects the passive electrical component and the one or more electrical contacts.Type: ApplicationFiled: February 12, 2019Publication date: March 18, 2021Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Scott WARRICK, cHRISTIAN LARSEN, Eric J. KING, John L. MELANSON, Anthony S. DOY, David M. BIVEN
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Patent number: 10586865Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.Type: GrantFiled: September 29, 2017Date of Patent: March 10, 2020Assignee: Cirrus Logic, Inc.Inventors: Scott Warrick, Justin Dougherty, Alexander Barr, Christian Larsen, Marc L. Tarabbia, Ying Ying
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Publication number: 20200006551Abstract: Embodiments described herein relate to a method of manufacture of an LDMOS transistor an LDMOS transistor, and an integrated circuit comprising an LDMOS transistor. The method of manufacture of the LDMOS device comprises implanting a Fluorine dopant in a drift region of the LDMOS device in order to improve alignment between the drift region of the LDMOS transistor and a thicker area of a single gate oxide layer grown on the drift region and a channel region of the LDMOS transistor.Type: ApplicationFiled: June 25, 2019Publication date: January 2, 2020Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Zhonghai SHI, Scott WARRICK
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Publication number: 20190103490Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Scott WARRICK, Justin DOUGHERTY, Alexander BARR, Christian LARSEN, Marc L. TARABBIA, Ying YING
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Patent number: 8435874Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.Type: GrantFiled: January 23, 2008Date of Patent: May 7, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Scott Warrick, Massud Abubaker Aminpur, Will Conley, Lionel Riviere-Cazeaux
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Patent number: 8187978Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, forming a main mask over the dielectric layer, the main mask comprising a plurality of main mask openings arranged in a regular pattern extending over the dielectric layer, using a selector mask to select some of the plurality of main mask openings and removing portions of the dielectric layer through the selected some of the plurality of main mask openings to provide openings extending through the dielectric layer to the layer.Type: GrantFiled: July 27, 2007Date of Patent: May 29, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Scott Warrick, Massud Abubaker Aminpur
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Patent number: 7948607Abstract: An immersion lithography apparatus includes an optical system having a liquid delivery unit. The liquid delivery unit is arranged to deliver a layer of an immersion liquid onto a surface of a wafer as well as an annulus of a barrier liquid adjacent an exterior wall of the immersion liquid. The presence of the barrier liquid prevents ingress to the immersion liquid of a gas external to the immersion liquid.Type: GrantFiled: December 22, 2005Date of Patent: May 24, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Scott Warrick, Kevin Cooper
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Patent number: 7837762Abstract: In the field of immersion lithography, it is known to provide a liquid between an optical exposure system and a wafer carrying layers of photosensitive material to be irradiated with a pattern by the optical exposure system. However, bubbles are known to form or exist in the liquid, sometimes close to a surface of the wafer resulting in scattering of light emitted from the optical exposure system. The scattering causes the pattern recorded in the layers of photosensitive material to be corrupted, resulting in defective wafers. Therefore, the present invention provides a bubble displacement apparatus comprising a drive signal generator for driving a force generator arranged to generate a force in response to a drive signal generated by the drive signal generator. The force generated urges the bubble away from the surface.Type: GrantFiled: May 17, 2005Date of Patent: November 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kevin Cooper, Scott Warrick
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Publication number: 20100291770Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.Type: ApplicationFiled: January 23, 2008Publication date: November 18, 2010Inventors: Scott Warrick, Massud Abubaker Aminpur, Will Conley, Lionel Riviere-Cazeaux
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Publication number: 20100193919Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, forming a main mask over the dielectric layer, the main mask comprising a plurality of main mask openings arranged in a regular pattern extending over the dielectric layer, using a selector mask to select some of the plurality of main mask openings and removing portions of the dielectric layer through the selected some of the plurality of main mask openings to provide openings extending through the dielectric layer to the layer.Type: ApplicationFiled: July 27, 2007Publication date: August 5, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Scott Warrick, Massud Abubaker Aminpur
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Publication number: 20090134496Abstract: A wafer comprises a multi-layer structure. The multi-layer structure includes a first device structure neighbouring an area for receiving alignment markers. A plurality of alignment markers extend into the multi-layer structure and are located within the area for receiving alignment markers. The plurality of alignment markers is arranged to prevent propagation of a crack, when occurring, beyond a material-dependent critical length in a part of the multi-layer structure corresponding to the area for receiving the alignment structure. The material-dependent critical length is associated with the part of the multi-layer structure.Type: ApplicationFiled: July 6, 2006Publication date: May 28, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Scott Warrick, Clyde Browning, Kevin Cooper, Cindy Goldberg, Brad Smith
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Publication number: 20090126565Abstract: In the field of immersion lithography, it is known to provide a liquid between an optical exposure system and a wafer carrying layers of photosensitive material to be irradiated with a pattern by the optical exposure system. However, bubbles are known to form or exist in the liquid, sometimes close to a surface of the wafer resulting in scattering of light emitted from the optical exposure system. The scattering causes the pattern recorded in the layers of photosensitive material to be corrupted, resulting in defective wafers. Therefore, the present invention provides a bubble displacement apparatus comprising a drive signal generator for driving a force generator arranged to generate a force in response to a drive signal generated by the drive signal generator. The force generated urges the bubble away from the surface.Type: ApplicationFiled: May 17, 2007Publication date: May 21, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Kevin Cooper, Scott Warrick
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Publication number: 20090002654Abstract: An immersion lithography apparatus comprises an optical system having a liquid delivery unit. The liquid delivery unit is arranged to deliver a layer of an immersion liquid onto a surface of a wafer as well as an annulus of a barrier liquid adjacent an exterior wall of the immersion liquid. The presence of the barrier liquid prevents ingress to the immersion liquid of a gas external to the immersion liquid.Type: ApplicationFiled: December 22, 2005Publication date: January 1, 2009Inventors: Scott Warrick, Kevin Cooper