Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract: A system including first voltage supply circuitry configured to provide a first voltage supply with spurious frequency content and second voltage supply circuitry configured to provide a second voltage supply without the spurious frequency content is provided. The system includes signal generation circuitry configured to generate a first digital signal using a clock signal and the first voltage supply and configured to cause the spurious frequency content on the first voltage supply and output circuitry configured to generate a second digital signal from the first digital signal synchronous with the clock signal using the second voltage supply.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: A receiver includes a first terminal for receiving an RF signal having a frequency of less than approximately 60 MHz, a second terminal, and a receive path having an input coupled to the first terminal and an output for providing a demodulated RF signal. The receiver further includes a detector coupled to the receive path for detecting a signal parameter in the RF signal and a controller coupled to the detector and to the second terminal. The controller provides the multiplex signal in a tuning state to the second terminal to selectively provide one of a first RF signal and a second RF signal to the first terminal and to determine at least one of a first parameter of the first RF signal and a second parameter of the second RF signal. The controller provides the multiplex signal in an operating state based on the first parameter and the second parameter.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: A system including first voltage supply circuitry configured to provide a first voltage supply with spurious frequency content and second voltage supply circuitry configured to provide a second voltage supply without the spurious frequency content is provided. The system includes signal generation circuitry configured to generate a first digital signal using a clock signal and the first voltage supply and configured to cause the spurious frequency content on the first voltage supply and output circuitry configured to generate a second digital signal from the first digital signal synchronous with the clock signal using the second voltage supply.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract: An oscillator includes a plurality of varactor cells to receive a control signal to control a frequency of the oscillator. Each of the varactor cells includes a switch that includes a first terninal to receive the control signal and a second terminal such that the switch operates to control a capacitance of the varactor cell in response to a voltage between the first and second terminals. The oscillator includes a bias circuit to provide a different bias voltage to each second terminal and an amplifier that is coupled to the varactor cells to generate an oscillating signal.

Abstract: A technique includes using a first stored energy source to generate a reference signal to circuitry of a supply regulator in response to the regulator being in a startup state. The technique includes using an output signal that is provided by the regulator to generate the reference signal in response to the regulator not being in the startup state.

Abstract: In one embodiment, the present invention includes an apparatus having a first capacitor coupled between a first node and a second node, a second capacitor coupled between the second node and a reference potential, and a third capacitor coupled between the second node and a switch, where the switch is controllable to couple the third capacitor to the second node. Using such an apparatus small changes in capacitance and correspondingly small changes in frequency may be effected. Other embodiments are directed to calibration of one or more capacitor banks.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract: A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for providing an output signal of the buffer (40); and a second transistor (45) having a first current electrode coupled to the second current electrode of the first transistor (44), a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for receiving a second power supply voltage. A capacitance of the capacitor (42) is chosen to reduce a peak-to-peak voltage swing of the input signal such that a peak-to-peak voltage swing at the control electrodes of the first (44) and second (45) transistors is less than or equal to a difference between the first and second power supply voltages.

Abstract: A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.