Abstract: A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: An envelope detection method by using a peel cone approximation concept and an envelope detection circuit which implements the envelope detection method are disclosed. The envelope detection circuit includes an absolute value-determining circuit, a maximum/minimum value-determining circuit, a plurality sets of comparison circuits, an address encoder, a read only memory (ROM), and a multiplier/adder. A delaying circuit for synchronization is further included in the envelope detection circuit. With the method and the circuit for an envelope detection by using a peel cone approximation, advantages of a compact circuit structure, less operation latency, a low approximation error and a low cost are all achieved.