Patents by Inventor Se A. Jang
Se A. Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949881Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.Type: GrantFiled: April 1, 2021Date of Patent: April 2, 2024Assignees: Electronics and Telecommunications Research Institute, Kwangwoon University Research Institute for Industry Cooperation, Industry-Academia Cooperation Group of Sejong UniversityInventors: Se-Yoon Jeong, Hae-Chul Choi, Jeong-Il Seo, Seung-Kwon Beack, In-Seon Jang, Jae-Gon Kim, Kyung-Ae Moon, Dae-Young Jang, Jin-Woo Hong, Jin-Woong Kim, Yung-Lyul Lee, Dong-Gyu Sim, Seoung-Jun Oh, Chang-Beom Ahn, Dae-Yeon Kim, Dong-Kyun Kim
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Patent number: 11942061Abstract: An electronic device includes a display panel that includes a first region including first pixel groups and a second region including second pixel groups, and a compensation circuit. The compensation circuit may receive first image data. The compensation circuit may compensate to generate second image data in response to a determination that the first image data corresponds to at least one of one or more particular first pixel groups that are adjacent to a boundary between the first region and the second region or one or more particular second pixel groups that are adjacent to the boundary. The compensation circuit outputs the second image data to the display panel.Type: GrantFiled: January 6, 2023Date of Patent: March 26, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Unki Park, Se Whan Na, Hyunwook Lim, Woohyuk Jang
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Publication number: 20240099113Abstract: An electronic device includes a display panel that includes a first region and a second region adjacent to the first region. The display panel includes a first light emitting unit that is disposed in the first region and that includes (1-1)th light emitting elements, (1-2)th light emitting elements, and (1-3)th light emitting elements and a second light emitting unit that is disposed in the first region and that includes (2-1)th light emitting elements, (2-2)th light emitting elements, and (2-3)th light emitting elements. The (1-1)th light emitting elements and the (2-1)th light emitting elements have the same arrangement pattern, the (1-3)th light emitting elements and the (2-3)th light emitting elements have the same arrangement pattern, and the (1-2)th light emitting elements and the (2-2)th light emitting elements have different arrangement patterns.Type: ApplicationFiled: June 27, 2023Publication date: March 21, 2024Applicant: Samsung Display Co., LTD.Inventors: MINWOO WOO, SUNGHO KIM, SE WAN SON, SEUNGHYUN LEE, WANGWOO LEE, JISEON LEE, KYEONGWOO JANG, HYERI CHO
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Publication number: 20160012956Abstract: Disclosed herein are a thin-type common mode filter and a manufacturing method thereof. According to an exemplary embodiment of the present invention, a thin-type common mode filter includes: a ferrite substrate having an upper surface on which irregular surface roughness is formed; an insulating layer formed on the upper surface of the ferrite substrate; and a conductive coil pattern formed in the insulating layer to be spaced apart from the upper surface of the ferrite substrate. Further, a manufacturing method of a thin-type common mode filter is proposed.Type: ApplicationFiled: July 11, 2014Publication date: January 14, 2016Inventors: Ju Hwan YANG, Young Seuck YOO, Geon Se JANG, Jong Yun LEE, Young Do KWEON, Sung Kwon WI
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Publication number: 20140139258Abstract: A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: Samsung Electronics Co., LtdInventors: Se-jang OH, Eun-jo BYUN, Cheol-jong WOO
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Patent number: 8674718Abstract: A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus.Type: GrantFiled: March 24, 2010Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., LtdInventors: Se-jang Oh, Eun-jo Byun, Cheol-jong Woo
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Patent number: 8606102Abstract: A test interface device includes a serializer, an optical transmitter, an optical receiver, and a deserializer. The serializer receives parallel test signals from automatic test equipment, and serializes the parallel test signals into a serial test signal. The optical transmitter converts the serial test signal into an optical test signal. The optical receiver receives the optical test signal from the optical transmitter, and converts the optical test signal into the serial test signal. The deserializer deserializes the serial test signal into the parallel test signals, and transmits the parallel test signals to a device under test. As a result, signal transfer speed may be improved and optical resource usage may be reduced.Type: GrantFiled: December 3, 2009Date of Patent: December 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Lee, Eun-Jo Byun, Cheol-Jong Woo, Se-Jang Oh
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Patent number: 8139949Abstract: An electrical signal transmission module includes a plurality of optical signal lines and a plurality of electrical signal lines. The plurality of optical signal lines converting a first externally input electrical signal into an optical signal, transmitting the optical signal, converting the optical signal back into the first electrical signal, and outputting the first electrical signal. The plurality of electrical signal lines transmitting a second externally input electrical signal and outputting the second electrical signal.Type: GrantFiled: July 24, 2008Date of Patent: March 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Lee, Ho-Jeong Choi, Se-Jang Oh, Young-Soo An, Gyu-Yeol Kim
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Patent number: 8026733Abstract: A wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board.Type: GrantFiled: June 2, 2009Date of Patent: September 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Lee, Chang-woo Ko, Young-soo An, Se-jang Oh
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Patent number: 7973550Abstract: A semiconductor device test apparatus is provided. The semiconductor device test apparatus includes a test unit on which a semiconductor device under test is disposed, and an automatic test equipment (ATE) unit that inputs a test signal to the test unit and reads a test result signal output by the test unit. The semiconductor device test apparatus includes an interface unit that is interposed between the test unit and the ATE unit, and that compares the test signal with the test result signal and outputs to the ATE unit comparison signals indicating whether the semiconductor device is a failure or not or whether a specific bit failure has occurred or not.Type: GrantFiled: October 21, 2009Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Jo Byun, Sang-Hoon Lee, Se-Jang Oh, Cheol-Jong Woo
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Patent number: 7884628Abstract: An interposer may include a first base, at least one first signal line in the first base, and at least one first ground line in the first base, wherein the ground line surrounds the at least one first signal line. The at least one first signal line and the at least one first ground line may be exposed through an upper surface of the first base. The at least one first signal line may be configured to conduct a test current through the first base. An interposer may also include a second base below the first base and may include a printed circuit board between the first base and the second base. A probe card may include a multilayer substrate having at least one contact needle, a coaxial board having at least one coaxial signal cable and the above described interposer between the multilayer substrate and the coaxial board.Type: GrantFiled: October 17, 2008Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Soo An, Sang-Hoon Lee, Se-Jang Oh
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Patent number: 7880490Abstract: A wireless interface probe card includes a substrate member and a transmission member. The substrate member has a plurality of probe terminals arranged at a constant pitch. The probe terminals may directly contact a plurality of pads arranged at a constant pitch on each of a plurality of semiconductor chips arranged on a wafer to perform a test of the semiconductor chips arranged on the wafer. The transmission member is arranged on the substrate member, wirelessly receives a test signal and provides the received test signal to the pads of the wafer through the probe terminals, and wirelessly and externally transmits an electrical characteristic signal provided from the pads of the wafer through the probe terminals.Type: GrantFiled: August 28, 2008Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Lee, Kwang-Yong Lee, Se-Jang Oh, Young-Soo An
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Publication number: 20100289517Abstract: A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus.Type: ApplicationFiled: March 24, 2010Publication date: November 18, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Se-jang OH, Eun-jo BYUN, Cheol-jong WOO
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Publication number: 20100182035Abstract: A semiconductor device test apparatus is provided. The semiconductor device test apparatus includes a test unit on which a semiconductor device under test is disposed, and an automatic test equipment (ATE) unit that inputs a test signal to the test unit and reads a test result signal output by the test unit. The semiconductor device test apparatus includes an interface unit that is interposed between the test unit and the ATE unit, and that compares the test signal with the test result signal and outputs to the ATE unit comparison signals indicating whether the semiconductor device is a failure or not or whether a specific bit failure has occurred or not.Type: ApplicationFiled: October 21, 2009Publication date: July 22, 2010Inventors: Eun-Jo Byun, Sang-Hoon Lee, Se-Jang Oh, Cheol-Jong Woo
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Publication number: 20100150549Abstract: A test interface device includes a serializer, an optical transmitter, an optical receiver, and a deserializer. The serializer receives parallel test signals from automatic test equipment, and serializes the parallel test signals into a serial test signal. The optical transmitter converts the serial test signal into an optical test signal. The optical receiver receives the optical test signal from the optical transmitter, and converts the optical test signal into the serial test signal. The deserializer deserializes the serial test signal into the parallel test signals, and transmits the parallel test signals to a device under test. As a result, signal transfer speed may be improved and optical resource usage may be reduced.Type: ApplicationFiled: December 3, 2009Publication date: June 17, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Lee, Eun-Jo Byun, Cheol-Jong Woo, Se-Jang Oh
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Publication number: 20100117673Abstract: A wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board.Type: ApplicationFiled: June 2, 2009Publication date: May 13, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Lee, Chang-woo Ko, Young-soo An, Se-jang Oh
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Publication number: 20100025682Abstract: In an interface device for wireless testing capable of testing a semiconductor chip in a non-contact manner, a semiconductor device and a semiconductor package including the same, and a method for wirelessly testing a semiconductor device using the same are provided, the interface device for wireless testing includes an interface substrate, interface antennas on the interface substrate, and interface transmitting and receiving circuits on the interface substrate, wherein the interface transmitting and receiving circuits are electrically connected to input/output pads of a semiconductor chip via interface vias passing through the interface substrate.Type: ApplicationFiled: August 3, 2009Publication date: February 4, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Hoon Lee, Eun-Jo Byun, Se-Jang Oh, Young-Soo An, Chang-Hyun Cho
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Publication number: 20090189624Abstract: An interposer and a probe card assembly for electrical die sorting is provided. The assembly may include probes electrically contacting pads of dies on a substrate, a first wiring unit including a first wire on and electrically contacting the probes, an interposer unit including interposers on the first wiring unit and electrically contacting the first wire, and a second wiring unit including a second wire on the interposer unit and electrically contacting the interposers. At least one interposer includes a conductive member, a first connection member adjacent to a first end of the conductive member so as to electrically connect the conductive member to the first wire, a second connection member adjacent to a second end of the conductive member so as to electrically connect the conductive member to the second wire, and at least one protrusion member on an external surface of the conductive member between the first and second connection members.Type: ApplicationFiled: September 26, 2008Publication date: July 30, 2009Inventors: Se-Jang Oh, Hal-young Lee, Young-soo An, Sang-hoon Lee, Sung-ho Joo, Dong-yeop Kim
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Patent number: 7538566Abstract: An electrical test system includes a test head, a performance board, a probe card and coaxial cables. The performance board includes a first side and an opposite second side, where the first side of the performance board is electrically connected to the test head and the second side of the performance board includes first coaxial cable connection portions. The probe card includes a first side and an opposite second side, where the first side of the probe card includes second coaxial cable connection portions and the second side includes a wafer test probes. The coaxial cables respectively electrically connect the first coaxial cable connection portions of the performance board to the second coaxial cable connection portions of the probe card.Type: GrantFiled: October 29, 2007Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Soo An, Se-Jang Oh, Jung-Hyun Nam
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Publication number: 20090102500Abstract: An interposer may include a first base, at least one first signal line in the first base, and at least one first ground line in the first base, wherein the ground line surrounds the at least one first signal line. The at least one first signal line and the at least one first ground line may be exposed through an upper surface of the first base. The at least one first signal line may be configured to conduct a test current through the first base. An interposer may also include a second base below the first base and may include a printed circuit board between the first base and the second base. A probe card may include a multilayer substrate having at least one contact needle, a coaxial board having at least one coaxial signal cable and the above described interposer between the multilayer substrate and the coaxial board.Type: ApplicationFiled: October 17, 2008Publication date: April 23, 2009Inventors: Young-Soo An, Sang-Hoon Lee, Se-Jang Oh