Patents by Inventor Se Ahn

Se Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7544935
    Abstract: A method for evaluating thin films comprises the steps of inputting measurement conditions, generating electron beams from an electron source to condense the electron beams to a specimen by a condenser lens, enlarging the electron beams transmitted by the specimen with imaging lenses to image an enlarged image of the specimen, acquiring elemental maps of the specimen with an element analyzer to display the acquired elemental maps, measuring a length of the elemental maps, and correcting the measurement conditions. Disclosed is an evaluating apparatus that implements the above evaluating method.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: June 9, 2009
    Assignees: Hitachi, Ltd., Hitachi High-Technologies Corporation, Samsung Electronics Co.
    Inventors: Shohei Terada, Kazutoshi Kaji, Tatsumi Hirano, Gyeong-su Park, Se-ahn Song, Jong-bong Park
  • Patent number: 7453111
    Abstract: Disclosed is a phase-change memory device including a phase-change material pattern, a diffusion barrier layer, a bottom electrode and a top electrode. The phase-change material pattern is placed on the bottom electrode, and the diffusion barrier layer containing tellurium is placed on the phase-change material pattern. The top electrode containing titanium is placed on the diffusion barrier layer. The diffusion barrier layer acts to inhibit diffusion of titanium from the top electrode into the phase-change material pattern.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: November 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Chang Ryoo, Ju-Chul Park, Se-Ahn Song, Yoon-Jong Song
  • Publication number: 20070284622
    Abstract: Disclosed is a phase-change memory device including a phase-change material pattern, a diffusion barrier layer, a bottom electrode and a top electrode. The phase-change material pattern is placed on the bottom electrode, and the diffusion barrier layer containing tellurium is placed on the phase-change material pattern. The top electrode containing titanium is placed on the diffusion barrier layer. The diffusion barrier layer acts to inhibit diffusion of titanium from the top electrode into the phase-change material pattern.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Chang Ryoo, Ju-Chul Park, Se-Ahn Song, Yoon-Jong SONG
  • Publication number: 20070161259
    Abstract: Disclosed herein is a method of fabricating a two dimensional (2D) nanostructure. The method includes heating a substrate within a vacuum chamber, injecting a metallic material into the vacuum chamber, adsorbing the metallic material on a surface of the substrate, and cooling the substrate to fabricate the 2D nanostructure on the surface of the substrate. The 2D nanostructures can be fabricated as monolayers.
    Type: Application
    Filed: October 11, 2006
    Publication date: July 12, 2007
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Se-ahn Song, Alexander V. Latyshev, Ludmila I. Fedina, Anton K. Gutakovskii, Sergey S. Kosolobov
  • Publication number: 20070077673
    Abstract: There is provided a method for manufacturing a vertically structured LED capable of performing a chip separation process with ease. In the method, a light-emitting structure is formed on a growth substrate having a plurality of device regions and at least one device isolation region, wherein the light-emitting structure has an n-type clad layer, an active layer and a p-type clad layer which are disposed on the growth substrate in sequence. A p-electrode is formed on the light-emitting structure. Thereafter, a first plating layer is formed on the p-electrode such that it connects the plurality of device isolation regions. A pattern of a second plating layer is formed on the first plating layer of the device region. The growth substrate is removed, and an n-electrode is then formed on the n-type clad layer.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 5, 2007
    Inventors: Hae Hwang, Yung Ryu, Da Shim, Se Ahn
  • Publication number: 20060268955
    Abstract: The invention provides a high-quality vertical semiconductor light emitting device having fewer cracks and a manufacturing method thereof. In the vertical semiconductor light emitting device, an Si—Al alloy substrate is prepared. Then a p-type group III-V compound semiconductor layer is formed on the Si—Al alloy substrate. An active layer is formed on the p-type group III-V compound semiconductor layer. Also, an n-type group III-V compound semiconductor layer is formed on the active layer.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 30, 2006
    Inventors: Myong Cho, Masayoshi Koike, Kyeong Min, Se Ahn, Hee Park
  • Publication number: 20060145075
    Abstract: A method for evaluating thin films comprises the steps of inputting measurement conditions, generating electron beams from an electron source to condense the electron beams to a specimen by a condenser lens, enlarging the electron beams transmitted by the specimen with imaging lenses to image an enlarged image of the specimen, acquiring elemental maps of the specimen with an element analyzer to display the acquired elemental maps, measuring a length of the elemental maps, and correcting the measurement conditions. Disclosed is an evaluating apparatus that implements the above evaluating method.
    Type: Application
    Filed: December 8, 2005
    Publication date: July 6, 2006
    Inventors: Shohei Terada, Kazutoshi Kaji, Tatsumi Hirano, Gyeong-su Park, Se-ahn Song, Jong-bong Park
  • Patent number: 7053372
    Abstract: A standard sample for transmission electron microscopy (TEM) elemental mapping and a TEM elemental mapping method using the same are provided. The standard sample includes a substrate; a first crystalline thin film containing heavy atoms formed on the substrate; a first amorphous thin film having oxides or nitrides containing light atoms and having a thickness of 1–5 nm or 6–10 nm formed on the first crystalline thin film; a second crystalline thin film containing heavy atoms formed on the first amorphous thin film. The standard sample can be used to correct TEM, EDS and EELS mapping results of a multi-layered nanometer-sized thin film and to optimize mapping conditions.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 30, 2006
    Assignees: Samsung Electronics Co., Ltd., Hitachi, Ltd., Hitachi High-Technologies Co.
    Inventors: Gyeong-su Park, Kazutoshi Kaji, Jong-bong Park, Shohei Terada, Tatsumi Hirano, Se-ahn Song
  • Publication number: 20060065535
    Abstract: Provided is a method of fabricating an oxide film on a substrate. The method includes: (a) placing an electrode adjacent to a first region of the substrate on which the oxide film is to be formed under a humid atmosphere; (b) contacting the electrode with the substrate while applying voltage between the electrode and the substrate; and (c) applying pressure to the electrode while applying voltage between the electrode and the substrate and forming the oxide film on the surface of the substrate due to anodic oxidation. Accordingly, the oxide film fabrication method may be used to fabricate an electronic device with a nanometer scale.
    Type: Application
    Filed: August 2, 2005
    Publication date: March 30, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ahn Song, Alexander Latyshev, Anton Gutakovskii, Dmitry Sheglov, Ludmila Fedina
  • Publication number: 20060033047
    Abstract: Embodiments include a method of forming a crystal surface with uniform monoatomic steps using metal adsorption. The method of controlling crystal surface morphology may include heating crystal to a predetermined temperature by applying a direct current (DC) voltage to its both ends; and depositing metal atoms to the crystal surface heated to a predetermined temperature at a predetermined depositing rate while maintaining the application of DC voltage so as to form monoatomic steps on the crystal surface.
    Type: Application
    Filed: July 21, 2005
    Publication date: February 16, 2006
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Se-ahn Song, Alexander Latyshev, Sergey Kosolobov, Anton Gutakovskii, Ludmila Fedina
  • Publication number: 20050184233
    Abstract: A standard sample for transmission electron microscopy (TEM) elemental mapping and a TEM elemental mapping method using the same are provided. The standard sample includes a substrate; a first crystalline thin film containing heavy atoms formed on the substrate; a first amorphous thin film having oxides or nitrides containing light atoms and having a thickness of 1-5 nm or 6-10 nm formed on the first crystalline thin film; a second crystalline thin film containing heavy atoms formed on the first amorphous thin film. The standard sample can be used to correct TEM, EDS and EELS mapping results of a multi-layered nanometer-sized thin film and to optimize mapping conditions.
    Type: Application
    Filed: January 14, 2005
    Publication date: August 25, 2005
    Applicants: Samsung Electronics Co., Ltd., Hitachi, Ltd., Hitachi High-Technologies Co.
    Inventors: Gyeong-su Park, Kazutoshi Kaji, Jong-bong Park, Shohei Terada, Tatsumi Hirano, Se-ahn Song