Patents by Inventor Se-Chung Oh
Se-Chung Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240284802Abstract: A magnetic memory device and a method for fabricating the same are provided. The magnetic memory device includes a pinned layer pattern, a free layer pattern including boron (B), a tunnel barrier layer pattern between the pinned layer pattern and the free layer pattern, an oxide layer pattern spaced apart from the tunnel barrier layer pattern with the free layer pattern therebetween, the oxide layer pattern including a metal borate, and a capping layer pattern spaced apart from the free layer pattern with the oxide layer pattern therebetween, the capping layer pattern including a metal boride, wherein a difference between a boron concentration of the free layer pattern and a boron concentration of the oxide layer pattern is 10 at % or less, and a difference between the boron concentration of the oxide layer pattern and a boron concentration of the capping layer pattern is 10 at % or less.Type: ApplicationFiled: September 5, 2023Publication date: August 22, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Hee Ju SHIN, Se Chung OH, Jun Ho JEONG
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Patent number: 11735241Abstract: A magnetic memory device includes a pinned layer, a free layer, a tunnel barrier layer between the pinned layer and the free layer, a first oxide layer spaced apart from the tunnel barrier layer with the free layer therebetween, and a second oxide layer spaced apart from the free layer with the first oxide layer therebetween. The first oxide layer includes an oxide of a first material and may have a thickness of 0.3 ? to 2.0 ?. The second oxide layer may include an oxide of a second material and may have a thickness of 0.1 ? to 5.0 ?. A first oxygen affinity of the first material may be greater than a second oxygen affinity of the second material.Type: GrantFiled: March 16, 2021Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee Ju Shin, Sang Hwan Park, Se Chung Oh, Ki Woong Kim, Hyeon Woo Seo
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Patent number: 11725271Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.Type: GrantFiled: April 15, 2022Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Woong Kim, Hyeon Woo Seo, Hee Ju Shin, Se Chung Oh, Hyun Cho
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Patent number: 11706931Abstract: A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.Type: GrantFiled: April 14, 2021Date of Patent: July 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Hoon Kim, Sang Hwan Park, Yong-Sung Park, Hyeonwoo Seo, Se Chung Oh, Hyun Cho
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Patent number: 11683992Abstract: A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.Type: GrantFiled: December 27, 2020Date of Patent: June 20, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyungjong Jeong, Ki Woong Kim, Younghyun Kim, Junghwan Park, Byoungjae Bae, Se Chung Oh, Jungmin Lee, Kyungil Hong
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Patent number: 11600662Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.Type: GrantFiled: January 24, 2022Date of Patent: March 7, 2023Inventors: Junghwan Park, Younghyun Kim, Se Chung Oh, Jungmin Lee, Kyungil Hong
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Publication number: 20220254994Abstract: A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.Type: ApplicationFiled: September 3, 2021Publication date: August 11, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kyungil HONG, Jungmin LEE, Younghyun KIM, Junghwan PARK, Heeju SHIN, Se Chung OH
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Publication number: 20220235450Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Woong KIM, Hyeon Woo SEO, Hee Ju SHIN, Se Chung OH, Hyun CHO
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Patent number: 11339467Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.Type: GrantFiled: February 18, 2020Date of Patent: May 24, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Woong Kim, Hyeon Woo Seo, Hee Ju Shin, Se Chung Oh, Hyun Cho
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Publication number: 20220149270Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Inventors: JUNGHWAN PARK, YOUNGHYUN KIM, SE CHUNG OH, JUNGMIN LEE, KYUNGIL HONG
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Patent number: 11293091Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.Type: GrantFiled: April 30, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Myoung Lee, Yong-Sung Park, Whan-Kyun Kim, Se-Chung Oh, Young-Man Jang
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Publication number: 20220102427Abstract: A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.Type: ApplicationFiled: April 14, 2021Publication date: March 31, 2022Inventors: Jae Hoon KIM, Sang Hwan PARK, Yong-Sung PARK, Hyeonwoo SEO, Se Chung OH, Hyun CHO
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Patent number: 11271037Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.Type: GrantFiled: February 27, 2020Date of Patent: March 8, 2022Inventors: Junghwan Park, Younghyun Kim, Se Chung Oh, Jungmin Lee, Kyungil Hong
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Publication number: 20220020409Abstract: A magnetic memory device includes a pinned layer, a free layer, a tunnel barrier layer between the pinned layer and the free layer, a first oxide layer spaced apart from the tunnel barrier layer with the free layer therebetween, and a second oxide layer spaced apart from the free layer with the first oxide layer therebetween. The first oxide layer includes an oxide of a first material and may have a thickness of 0.3 ? to 2.0 ?. The second oxide layer may include an oxide of a second material and may have a thickness of 0.1 ? to 5.0 ?. A first oxygen affinity of the first material may be greater than a second oxygen affinity of the second material.Type: ApplicationFiled: March 16, 2021Publication date: January 20, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hee Ju SHIN, Sang Hwan PARK, Se Chung OH, Ki Woong KIM, Hyeon Woo SEO
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Publication number: 20210359198Abstract: A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.Type: ApplicationFiled: December 27, 2020Publication date: November 18, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: HYUNGJONG JEONG, KI WOONG KIM, YOUNGHYUN KIM, JUNGHWAN PARK, BYOUNGJAE BAE, SE CHUNG OH, JUNGMIN LEE, KYUNGIL HONG
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Patent number: 11170832Abstract: A magnetic memory device includes a first conductive line extending in a first direction on a substrate, a first magnetic pattern on the first conductive line, the first magnetic pattern including a first portion and a second portion that have different thicknesses, and a second conductive line on the first magnetic pattern and extending in a second direction intersecting the first direction.Type: GrantFiled: August 27, 2019Date of Patent: November 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Woong Kim, Juhyun Kim, Se Chung Oh, Ung Hwan Pi
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Publication number: 20210010127Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.Type: ApplicationFiled: February 18, 2020Publication date: January 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Woong Kim, Hyeon Woo Seo, Hee Ju Shin, Se Chung Oh, Hyun Cho
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Publication number: 20210013261Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.Type: ApplicationFiled: February 27, 2020Publication date: January 14, 2021Inventors: JUNGHWAN PARK, YOUNGHYUN KIM, SE CHUNG OH, JUNGMIN LEE, KYUNGIL HONG
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Publication number: 20200255934Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Inventors: Joon-Myoung LEE, Yong-Sung PARK, Whan-Kyun KIM, Se-Chung OH, Young-Man JANG
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Patent number: 10714678Abstract: The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.Type: GrantFiled: December 27, 2019Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sung Park, Woo-Jin Kim, Jeong-Heon Park, Se-Chung Oh, Joon-Myoung Lee, Hyun Cho