Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.

Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.

Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.

Abstract: A sense amplifying circuit capable of operating with a lower voltage and/or a nonvolatile memory device including the same may be provided. The nonvolatile memory device may include a nonvolatile memory cell array including a first bit line connected with a first memory cell and/or a second bit line connected with a first reference memory cell, and/or a sense amplifying circuit configured to sense data stored in the first memory cell based on a current flowing in the first bit line and/or a current flowing in the second bit line.

Abstract: A boost voltage generating circuit and method thereof. The example boost voltage generating circuit may include a voltage comparator comparing an input voltage and a reference voltage and generating a control signal based on a result of the voltage comparison, the input voltage based on a feedback boost voltage, a voltage generator generating a boost voltage in response to the control signal and a boost voltage controller including a first resistor with a first end connected to the boost voltage and a second end connected to the voltage comparator, the boost voltage controller controlling a level of current flowing through the first resistor based on one of a number of memory cells to be programmed and a number of cell groups including at least one memory cell to be programmed.

Abstract: A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and performing high-speed level shifting by increasing the speed of charging electric charges into or discharging electric charges from an output terminal of a differential amplification circuit included in the level shifter.

Abstract: A sense amplifying circuit capable of operating with a lower voltage and/or a nonvolatile memory device including the same may be provided. The nonvolatile memory device may include a nonvolatile memory cell array including a first bit line connected with a first memory cell and/or a second bit line connected with a first reference memory cell, and/or a sense amplifying circuit configured to sense data stored in the first memory cell based on a current flowing in the first bit line and/or a current flowing in the second bit line.

Abstract: A boost voltage generating circuit and method thereof. The example boost voltage generating circuit may include a voltage comparator comparing an input voltage and a reference voltage and generating a control signal based on a result of the voltage comparison, the input voltage based on a feedback boost voltage, a voltage generator generating a boost voltage in response to the control signal and a boost voltage controller including a first resistor with a first end connected to the boost voltage and a second end connected to the voltage comparator, the boost voltage controller controlling a level of current flowing through the first resistor based on one of a number of memory cells to be programmed and a number of cell groups including at least one memory cell to be programmed.

Abstract: In a flash memory device and a bit line voltage control method thereof a circuit capable of reducing the change in a voltage of a bit line during programming. The flash memory device includes: a flash memory cell, a source of which is connected to a source line, a drain of which is connected to a bit line and a gate of which is connected to a word line; a word line voltage generation circuit connected to the word line, for generating and providing a word line voltage to the word line; a program current generation circuit connected to the bit line, for generating and providing a program current to the bit line; and a bit line voltage clamp circuit connected to the bit line and the word line, for sensing a voltage of the bit line and controlling a bias current of the word line voltage generation circuit to thereby control a voltage of the bit line, during a programming operation of the flash memory device.

Abstract: In a flash memory device and a bit line voltage control method thereof a circuit capable of reducing the change in a voltage of a bit line during programming. The flash memory device includes: a flash memory cell, a source of which is connected to a source line, a drain of which is connected to a bit line and a gate of which is connected to a word line; a word line voltage generation circuit connected to the word line, for generating and providing a word line voltage to the word line; a program current generation circuit connected to the bit line, for generating and providing a program current to the bit line; and a bit line voltage clamp circuit connected to the bit line and the word line, for sensing a voltage of the bit line and controlling a bias current of the word line voltage generation circuit to thereby control a voltage of the bit line, during a programming operation of the flash memory device.

Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.

Abstract: The present invention relates to a flash memory device. Cell currents of an over-erased flash memory cell and cell currents of a plurality of weakly-programmed flash memory cells are compared by a plurality of comparators, and an low-voltage detector and a plurality of charge pump circuits are driven depending on the comparison result. Accordingly, a circuit that is not affected by variation in temperature, power supply voltage and process can be implemented. The threshold voltages of the flash memory cells are controlled to adjust a low-voltage detection point or a regulation point.

Abstract: The present invention relates to a flash memory device. Cell currents of an over-erased flash memory cell and cell currents of a plurality of weakly-programmed flash memory cells are compared by a plurality of comparators, and an low-voltage detector and a plurality of charge pump circuits are driven depending on the comparison result. Accordingly, a circuit that is not affected by variation in temperature, power supply voltage and process can be implemented. The threshold voltages of the flash memory cells are controlled to adjust a low-voltage detection point or a regulation point.

Abstract: The present invention relates to a low voltage detector. The low voltage detector comprises a first flash memory cell driven by a ground voltage, for maintaining the potential of a first node to a given potential; a second flash memory cell driven by a power supply voltage, for controlling the potential of a second node; and a comparator for comparing the potentials of the first node and the second node. The difference in current between the first over-erased flash memory cell and the second weakly-programmed flash memory cell is sensed instead of using the reference voltage generator. Thus, a low voltage to be sensed can be freely determined by controlling a cell current. Further, according to the present invention, a constant current can be secured without being affected by change in the supply voltage using the over-erased flash memory cell.