Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Disclosed are a connector and a solar cell module including the same. The connector includes a body, and a connecting part received in the body. The connecting part is movably provided at an inside of the body and an outside of the body. The solar cell module includes a plurality of solar cell modules, a cable to connect the solar cell modules to each other, and a connector at an end portion of the cable. The connector includes a body, and a connecting part received in the body. The connecting part is movably provided at an inside of the body and an outside of the body. The solar cell module includes a first solar cell module including a first cable and a first connector, and a second solar cell module including a second cable and a second connector. The first connector includes a first body, a first connecting part received in the first body, a first fixing part, and a first-first groove and a first-second groove provided in the first connecting part.

Abstract: A solar cell includes a support substrate, a back electrode layer on the support substrate, a light absorbing layer on the back electrode layer, a buffer layer on the light absorbing layer, a high resistance buffer layer on the buffer layer, and a front electrode layer on the high resistance buffer layer. An insulating part is located on a top surface of the light absorbing layer. A method of fabricating the solar cell includes forming the back electrode layer on the substrate, forming the light absorbing layer on the back electrode layer, forming the buffer layer on the light absorbing layer, oxidizing a top surface of the buffer layer, and forming the front electrode layer on the buffer layer.

Abstract: Disclosed is a solar cell apparatus. The solar cell apparatus includes a solar cell panel; a protective substrate formed on the solar cell panel such that a step difference is formed between the protective substrate and the solar cell panel; and a sealing member at a lateral side of the solar cell panel and on a bottom surface of the protective substrate.

Abstract: Disclosed is a solar cell module. The solar cell module includes a solar cell panel including a plurality of solar cells; a protective substrate on the solar cell panel; and a ventilation unit for ventilating the solar cell panel.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

Abstract: Provided is a solar cell. The solar cell includes: a substrate including through lines opposing to each other; a semiconductor layer on a top side of the substrate; bus lines at both edges of a top side of the semiconductor layer; and bus bars connected electrically to the bus lines, respectively, and extending to a rear side of the substrate through the through lines.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: Disclosed are a solar cell apparatus and a method of fabricating the same. The solar cell apparatus includes a substrate, a back electrode layer on the substrate, a light absorbing layer on the back electrode layer, a front electrode layer on the light absorbing layer, a bus bar provided beside the light absorbing layer while being connected to the back electrode layer, and a conductive part surrounding the bus bar. The method includes forming a back electrode layer on a substrate, forming a bus bar on the back electrode layer, forming a light absorbing layer beside the bus bar on the back electrode layer, and forming a front electrode layer on the light absorbing layer. A conductive part surrounds the bus bar in the step of forming the bus bar.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: Disclosed are a solar cell module and a method of fabricating the same. The solar cell module includes a solar cell panel; a protective substrate on the solar cell panel; a buffer portion between the solar cell panel and the protective substrate; a frame surrounding the solar cell panel and receiving the solar cell panel therein; and a sealing portion between the solar cell panel and the frame, wherein the sealing portion extends from the buffer portion. The method of fabricating a solar cell module includes the steps: preparing a solar cell panel; preparing a protective substrate on the solar cell panel; preparing a filler between the solar cell panel and the protective substrate; placing a frame that receives the solar cell panel and the protective substrate therein; and laminating the filler, wherein the laminating of the filler is performed after the placing of the frame.