Abstract: The non-volatile memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: There are provided a method of operating a voltage generator. The method includes providing a reference voltage, sensing a magnitude of a charge current for increasing voltages of a plurality of word lines based on the reference voltage, determining whether the sensed magnitude of the charge current is greater than a peak current value, increasing the reference voltage in accordance with a first slope when the sensed magnitude of the charge current is less than or equal to the peak current value, and increasing the reference voltage in accordance with a second slope less than the first slope when the detected magnitude of the charge current is greater than the peak current value.

Abstract: The memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: The non-volatile memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: There are provided a method of operating a voltage generator. The method includes providing a reference voltage, sensing a magnitude of a charge current for increasing voltages of a plurality of word lines based on the reference voltage, determining whether the sensed magnitude of the charge current is greater than a peak current value, increasing the reference voltage in accordance with a first slope when the sensed magnitude of the charge current is less than or equal to the peak current value, and increasing the reference voltage in accordance with a second slope less than the first slope when the detected magnitude of the charge current is greater than the peak current value.

Abstract: The memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Abstract: A programming method of a non-volatile memory device including a plurality of memory cells arranged in a plurality of cell strings includes sequentially applying a first pass voltage to unselected word lines of word lines connected to the plurality of memory cells during a first interval and a second pass voltage higher than the first pass voltage to the unselected word lines during a second interval; and applying a discharge voltage lower than a program voltage to a selected word line of the word lines connected to the plurality of memory cells after applying the program voltage to the selected word line in the first interval, and applying the program voltage to the selected word line during the second interval.

Abstract: A data read operation method of a memory device includes applying a read voltage having a first preparation level and a first target level to a word line of a selected cell in the memory device to read a program state of the selected cell, applying a first read pass voltage having a second preparation level and a second target level to at least one word line of first non-selected cells not adjacent to the selected cell and in the same string as the selected cell, and applying a second read pass voltage having a third target level to a word line of at least one second non-selected cell adjacent to the selected cell.

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Abstract: A programming method of a non-volatile memory device including a plurality of memory cells arranged in a plurality of cell strings includes sequentially applying a first pass voltage to unselected word lines of word lines connected to the plurality of memory cells during a first interval and a second pass voltage higher than the first pass voltage to the unselected word lines during a second interval; and applying a discharge voltage lower than a program voltage to a selected word line of the word lines connected to the plurality of memory cells after applying the program voltage to the selected word line in the first interval, and applying the program voltage to the selected word line during the second interval.

Abstract: A data read operation method of a memory device includes applying a read voltage having a first preparation level and a first target level to a word line of a selected cell in the memory device to read a program state of the selected cell, applying a first read pass voltage having a second preparation level and a second target level to at least one word line of first non-selected cells not adjacent to the selected cell and in the same string as the selected cell, and applying a second read pass voltage having a third target level to a word line of at least one second non-selected cell adjacent to the selected cell.