Patents by Inventor Se-Ho Cha

Se-Ho Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312147
    Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
    Type: Application
    Filed: December 24, 2018
    Publication date: October 10, 2019
    Inventors: Yong Su Lee, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang, Dae Ho Kim, Jae Neung Kim, Myoung Geun Cha, Sang Gab Kim, Yu-Gwang Jeong
  • Patent number: 10242880
    Abstract: Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive. The first additive and the second additive are separately supplied to the process bath.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangsu Kim, Se-Ho Cha, Yongsun Ko, Keonyoung Kim, Kyunghyun Kim, ChangSup Mun, Choongkee Seong, Sunjoong Song, Jinwoo Lee, Hoon Han
  • Patent number: 9972638
    Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghae Lee, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
  • Publication number: 20180102254
    Abstract: Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive.
    Type: Application
    Filed: July 10, 2017
    Publication date: April 12, 2018
    Inventors: Kwangsu Kim, Se-Ho CHA, Yongsun KO, Keonyoung KIM, Kyunghyun KIM, ChangSup MUN, Choongkee SEONG, Sunjoong SONG, Jinwoo LEE, Hoon HAN
  • Patent number: 9368647
    Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: June 14, 2016
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Young-Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
  • Publication number: 20150348799
    Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Young Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
  • Patent number: 9136120
    Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: September 15, 2015
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Young Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
  • Publication number: 20150162344
    Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
    Type: Application
    Filed: February 13, 2015
    Publication date: June 11, 2015
    Inventors: Sunghae LEE, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
  • Publication number: 20150104932
    Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Inventors: Young Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
  • Patent number: 8963231
    Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunghae Lee, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 8940182
    Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 27, 2015
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Young-Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
  • Patent number: 8765551
    Abstract: According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youl Yang, Dae-hong Eom, Byoung-moon Yoon, Kyung-hyun Kim, Se-ho Cha
  • Patent number: 8685821
    Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
  • Publication number: 20140004676
    Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 2, 2014
    Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 8552489
    Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
  • Publication number: 20130171788
    Abstract: According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 4, 2013
    Inventors: Jun-youl YANG, Dae-hong EOM, Byoung-moon YOON, Kyung-hyun KIM, Se-ho CHA
  • Publication number: 20130134493
    Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 30, 2013
    Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
  • Publication number: 20130092872
    Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
    Type: Application
    Filed: August 31, 2012
    Publication date: April 18, 2013
    Inventors: Young-Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
  • Publication number: 20120248525
    Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
    Type: Application
    Filed: February 21, 2012
    Publication date: October 4, 2012
    Inventors: Sunghae LEE, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 7527921
    Abstract: Example embodiments of the present invention relate to methods of treating and removing a photoresist pattern and a method of manufacturing a semiconductor device using the same. Other example embodiments of the present invention relate to a method of treating a photoresist pattern and a method of removing a photoresist pattern formed using a photoresist composition suitable for argon fluoride (ArF). In a method of removing a photoresist pattern, an ozone vapor including a water vapor and an ozone gas may be provided onto the photoresist pattern to remove a hydrophobic group from a photoresist resin included in the photoresist pattern. A cleaning solution may be provided to make the photoresist pattern water-soluble. A cleaning process may be performed on the photoresist pattern to remove the photoresist pattern. The photoresist pattern may be effectively removed without an increased processing time and/or damage to a substrate.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: May 5, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Chung, Dae-Keun Kang, Se-Ho Cha