Patents by Inventor Se-Ho You
Se-Ho You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11855013Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.Type: GrantFiled: June 7, 2022Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-Ho You, Seongho Shin, Bangweon Lee
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Publication number: 20230260887Abstract: A semiconductor package includes a first substrate including a first wiring layer inside the first substrate, a second substrate including a second wiring layer inside the second substrate, and a mold layer between the first substrate and the second substrate. An upper surface of the mold layer is on a same plane as upper surfaces of the first substrate and the second substrate. The package includes a first connecting film on each of the upper surface of the first substrate and the upper surface of the second substrate, the first connecting film connecting the first substrate and the second substrate, and a first semiconductor chip on the upper surface of the first substrate. The first semiconductor chip is spaced apart from the first connecting film, and an upper surface of the first connecting film is lower than an upper surface of the first semiconductor chip.Type: ApplicationFiled: September 6, 2022Publication date: August 17, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Se-Ho YOU, Ji-Yong PARK
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Publication number: 20230215824Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.Type: ApplicationFiled: March 10, 2023Publication date: July 6, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Se Ho YOU, Hyeong Seob Kim, Seung Kon Mok
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Publication number: 20230133977Abstract: A semiconductor device including a substrate and first and second packages thereon, the first package includes a first lower redistribution layer; a first core semiconductor stack thereon and including a first core chip and a first through via stacked on the first lower redistribution layer; and a first memory semiconductor stack on the first lower redistribution layer and including first memory chips stacked on the first lower redistribution layer, the second package includes a second lower redistribution layer; a second core semiconductor stack thereon and including a second core chip on the second lower redistribution layer; and a second memory semiconductor stack on the second lower redistribution layer and including second memory chips stacked on the second lower redistribution layer, the first through via penetrates the first core semiconductor stack, and the first and second lower redistribution layers are electrically connected to each other through the first through via.Type: ApplicationFiled: June 10, 2022Publication date: May 4, 2023Inventors: Se-Ho YOU, Ju-Il CHOI
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Patent number: 11626373Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.Type: GrantFiled: February 10, 2021Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Se Ho You, Hyeong Seob Kim, Seung Kon Mok
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Patent number: 11482509Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.Type: GrantFiled: June 19, 2020Date of Patent: October 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-Ho You, Kyung Suk Oh, Sunkyoung Seo
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Publication number: 20220302052Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.Type: ApplicationFiled: June 7, 2022Publication date: September 22, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: SE-HO YOU, SEONGHO SHIN, BANGWEON LEE
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Patent number: 11380635Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.Type: GrantFiled: December 15, 2020Date of Patent: July 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-Ho You, Seongho Shin, Bangweon Lee
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Publication number: 20210398924Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.Type: ApplicationFiled: February 10, 2021Publication date: December 23, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Se Ho YOU, Hyeong Seob KIM, Seung Kon MOK
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Publication number: 20210335734Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.Type: ApplicationFiled: December 15, 2020Publication date: October 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: SE-HO YOU, SEONGHO SHIN, BANGWEON LEE
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Publication number: 20210167040Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.Type: ApplicationFiled: June 19, 2020Publication date: June 3, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: SE-HO YOU, KYUNG SUK OH, SUNKYOUNG SEO
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Patent number: 10256181Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.Type: GrantFiled: July 6, 2018Date of Patent: April 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: JinGyu Kim, Taehun Kim, JiSun Hong, Byungmoon Bae, Se-Ho You
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Publication number: 20180315698Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.Type: ApplicationFiled: July 6, 2018Publication date: November 1, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: JinGyu Kim, Taehun Kim, JiSun Hong, Byungmoon Bae, Se-Ho You
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Patent number: 10032706Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.Type: GrantFiled: August 15, 2016Date of Patent: July 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: JinGyu Kim, Taehun Kim, JiSun Hong, Byungmoon Bae, Se-Ho You
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Publication number: 20170077041Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.Type: ApplicationFiled: August 15, 2016Publication date: March 16, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: JinGyu KIM, Taehun KIM, JiSun HONG, Byungmoon BAE, Se-Ho YOU
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Patent number: 9520387Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.Type: GrantFiled: October 2, 2014Date of Patent: December 13, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon Kim, Hee-Seok Lee, Seong-Ho Shin, Se-Ho You, Yun-Hee Lee
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Patent number: 9171827Abstract: A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.Type: GrantFiled: January 6, 2014Date of Patent: October 27, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Ho Lee, Hee-Seok Lee, Se-Ho You, Jeong-Oh Ha
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Patent number: 9147643Abstract: Provided is a semiconductor package which may include a package substrate which includes a power supply region and an interconnection region around the power supply region, a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate, and at least one semiconductor chip mounted on the package substrate, the semiconductor chip includes a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals.Type: GrantFiled: April 24, 2014Date of Patent: September 29, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: SE-Ho You, Jinho Lee
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Patent number: 9030838Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.Type: GrantFiled: January 3, 2014Date of Patent: May 12, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Ho You, Heeseok Lee, Chiyoung Lee, Yun-Hee Lee
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Publication number: 20150024545Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.Type: ApplicationFiled: October 2, 2014Publication date: January 22, 2015Inventors: Yong-Hoon KIM, Hee-Seok LEE, Seong-Ho SHIN, Se-Ho YOU, Yun-Hee LEE