Abstract: The present invention relates to a biomarker for predicting immunotherapy responsiveness in a patient with lung cancer and a use thereof, and more specifically, to a marker composition for predicting immunotherapy responsiveness in a patient with lung adenocarcinoma, a composition for predicting immunotherapy responsiveness, and a method for providing information for predicting immunotherapy responsiveness, comprising a CXCL13 gene or a protein encoded by the gene, and it was confirmed that CXCL3 was significantly upregulated in a patient administered an immune checkpoint inhibitor using the composition of the present invention, and through this, the CXCL13 gene or the protein encoded by the gene may be usefully used as a marker for predicting anticancer drug therapy responsiveness against lung cancer in related research fields, and is expected to be utilized as an immunotherapeutic adjuvant which enhances the anticancer treatment effect by developing an enhancer.

Abstract: The present invention provides an organic electroluminescent element and electronic device thereof, wherein the organic electroluminescent element comprises the compound represented by Formula 1 as material for an emission-auxiliary layer, and by comprising the compound represented by Formula 1 in the emission-auxiliary layer, the driving voltage of the organic electroluminescent element can be lowered, and the luminous efficiency and life time of the organic electroluminescent element can be improved.

Abstract: The present invention relates to a recording medium having data recorded therein in a data file format structure for visualization of large capacity CFD parallel data and to a method for generating said data file format structure, in which the large capacity data is generated and stored or recorded in the data file format structure of a structured grid or an unstructured grid in processing large capacity CFD data in parallel to each other and visualizing the data.

Abstract: In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: Provided are a display device with improved display quality and a method of driving the same. The display device includes: a display panel which includes a plurality of dither blocks displaying an image that corresponds to a dither image signal; and an image signal controller which generates the dither image signal by using a dither pattern that determines a plurality of dither pixels, which are to be dithered, from among a plurality of pixels included in each of the dither blocks, wherein each of the dither blocks includes a plurality of pixels, whose respective polarities are inverted every frame and which are driven accordingly, and comprises equal numbers of positive-polarity dither pixels and negative-polarity dither pixels.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

Abstract: In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

Abstract: A liquid crystal display device includes a timing controller generating a voltage compensation control pulse and a gate control signal, a voltage compensation signal generator generating a voltage compensation signal, the voltage level of which is gradually reduced during one frame period, in response to the voltage compensation control pulse, a power unit outputting a gate-on voltage to a plurality of gate lines by gradually increasing the level of the gate-on voltage in response to the voltage compensation signal, and a gate driver sequentially supplying the gate-on voltage to the plurality of gate lines in response to the gate control signal.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Abstract: In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

Abstract: A liquid crystal display device includes a timing controller generating a voltage compensation control pulse and a gate control signal, a voltage compensation signal generator generating a voltage compensation signal, the voltage level of which is gradually reduced during one frame period, in response to the voltage compensation control pulse, a power unit outputting a gate-on voltage to a plurality of gate lines by gradually increasing the level of the gate-on voltage in response to the voltage compensation signal, and a gate driver sequentially supplying the gate-on voltage to the plurality of gate lines in response to the gate control signal.