Abstract: A nanocrystal display device includes a plurality of pixels; a gate line extended in a row direction; a data line extended in a column direction; and a second insulating layer on the data line. Each pixel includes first and second pixel areas adjacent to each other in the column direction; first and second pixel electrodes on the second insulating layer of the first and second pixel areas; a first black matrix on the second insulating layer, and having a step difference greater than that of the first and second pixel electrodes; a common electrode extended in the row direction, contacting the first black matrix and spaced apart from the second insulating layer in the first and second pixel areas, and a tunnel-shaped cavity between the common electrode, the first black matrix and the second insulating layer; and a liquid crystal layer in the tunnel-shaped cavity.

Abstract: A liquid crystal display includes a first pixel and a second pixel that extend in a data line direction. The first and second pixels are connected to a same data line, and the first pixel is closer to a data driver than the second pixel. A channel width of a thin film transistor of the first pixel is less than a channel width of a thin film transistor of the second pixel.

Abstract: A display apparatus includes a display panel, a gate driving part, and a date driving part. The display panel includes a switching element disposed in association with a pixel, a main gate line connected to the switching element, and a sub gate line spaced apart from the main gate line and connected to the main gate line via a first connecting part. The gate driving part is configured to: provide the main gate line with a main gate signal, and provide the sub gate line with a sub gate signal. The sub gate signal includes a transmission difference from the main gate signal. The data driving part is configured to provide a data line with a data signal.

Abstract: A display panel includes: a first pixel including: a first high pixel configured to represent a first high gray level; and a first low pixel configured to represent a first low gray level; and a second pixel adjacent the first pixel in a first direction, the second pixel including: a second high pixel configured to represent a second high gray level based on a second data voltage and the common voltage in response to the first gate signal; and a second low pixel configured to represent a second low gray level based on the second data voltage, the common voltage, and a second divided voltage different from the first divided voltage in response to the first gate signal.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.

Abstract: A nano crystal display includes a display panel including a display area and a non-display area, a data driver which applies data voltages to pixels through data lines, a gate driver disposed in the non-display area and which sequentially applies gate signals to the pixels through gate lines in response to control signals, a control signal line part disposed in the non-display area and which applies the control signals to the gate driver, a cover layer which extends in a column direction and covers the gate driver and the control signal line part, and a sub-electrode which extends in the column direction and covers the cover layer. The pixels display gray scales corresponding to the data voltages provided through the data lines in response to the gate signals.

Abstract: A thin film transistor array panel includes a substrate, a gate line extending in a first direction on the substrate, a data line extending in a second direction on the substrate and intersecting the gate line, a thin film transistor connected to the gate line and the data line, an insulating layer on the gate line, the data line, and the thin film transistor, a first auxiliary line on the insulating layer and connected to the gate line, a second auxiliary line on the insulating layer and connected to the data line, and a pixel electrode connected to the thin film transistor.

Abstract: A thin film transistor array panel including a first substrate, a gate conductor on the first substrate, a data conductor on the gate conductor, a shielding electrode on the data conductor and insulated from the data conductor, a passivation layer on the shielding electrode, and a pixel electrode on the passivation layer, in which the shielding electrode includes a vertical portion vertically extending along an edge of a pixel area and overlapped with the data line, and one or more horizontal portions connecting the vertical portions.

Abstract: A display panel includes a gate line which extends substantially in a first direction, a first data line which extends substantially in a second direction substantially perpendicular to the first direction, a second data line spaced apart from the first data line in the first direction and which extends substantially in the second direction, a high pixel electrode disposed between the first data line and the second data line and disposed adjacent to the gate line, a low pixel electrode disposed between the first data line and the second data line and disposed opposite to the high pixel electrode with reference to the gate line, a high storage line which extends substantially in the second direction and overlaps the high pixel electrode, and a low storage line which extends substantially in the second direction and overlaps the low pixel electrode.

Abstract: A liquid crystal display includes a first insulation substrate; a gate line disposed on the first insulation substrate; a dividing reference voltage line disposed on the first insulation substrate; and a data line disposed on the first insulation substrate; a first switching element connected to the gate line, the data line and a first liquid crystal capacitor; a second switching element connected to the gate line, the data line and a second liquid crystal capacitor; a third switching element connected to the gate line, the second liquid crystal capacitor and the third liquid crystal capacitor; and a fourth switching element connected to the gate line, a third liquid crystal capacitor and the dividing reference voltage line.

Abstract: A gate drive circuit includes a shift register having a plurality of stages, in which an n-th stage (‘n’ is a natural number) of the plurality of stages is connected to at least one subsequent stage. The n-th stage includes a pull-up part configured to output a high voltage of an n-th gate signal using a high voltage of a clock signal as in response to a high voltage of a control node, a control pull-down part configured to pull-down a voltage of the control node into a low voltage in response to a carry signal outputted from at least one of next stages of the n-th stage and receiving a back-bias voltage corresponding to the low voltage, and a carry part configured to output the high voltage of the clock signal as an n-th carry signal in response to a high voltage of the control node.

Abstract: A display panel includes a gate line, a first data line crossing the gate line, a first voltage applied to the first data line, a second data line in parallel with the first data line and spaced apart from the first data line, a second voltage different from the first voltage applied to the second data line, a first thin film transistor electrically connected to the first data line, a second thin film transistor electrically connected to the second data line, a first pixel electrode electrically connected to the first thin film transistor, and disposed between the first data line and the second data line, and a second pixel electrode electrically connected to the second thin film transistor, and disposed opposite to the first pixel electrode with reference to the second data line.

Abstract: A liquid crystal display includes a gate line, data lines transmitting a first voltage; a transmitting line transmitting a second voltage; and pixels including first and second pixel electrodes. One pixel electrode receives the first voltage through a data line, and the other receives the second voltage through the transmitting line. Branch electrodes of the pixel electrodes alternate, and a stem of the first pixel electrode of a first pixel, faces a stem of the first pixel electrode of a second pixel and a stem of the second pixel electrode of the second pixel, with respect to the data line. Areas of the stem of the first pixel electrode of the second pixel facing the stem of the first pixel electrode of the first pixel, and of the stem of the second pixel electrode of the second pixel facing the stem of the first pixel, are the same.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.

Abstract: A display panel includes a plurality of pixels which is arranged in a pixel column and a pixel row, a gate line which is connected to pixels in a same pixel row, a first data line which is connected to pixels in a same pixel column, and a second data line which is connected to remaining pixels except for the pixels connected to the first data line among the pixels in the same pixel column. Two odd-numbered pixel rows and two even-numbered pixel rows are alternately driven so that a charge period of the pixel may be extended by 2H. In addition, a kickback difference between the odd-numbered pixel row and the even-numbered pixel row may be decreased so that a display quality may be improved.

Abstract: Provided is a liquid crystal display. The liquid crystal display includes: a substrate; a gate line, a common electrode line and a data line formed on the substrate; an insulating layer formed on the gate line, the common electrode line and the data line; a pixel electrode formed on the insulating layer; a microcavity formed on the pixel electrode and including a liquid crystal injection hole; a common electrode formed on the microcavity; a support member formed on the common electrode; and a capping layer formed on the support member and covering the liquid crystal injection hole, in which the common electrode line and the common electrode are connected to each other through a contact hole formed in a passivation layer.

Abstract: A display apparatus includes a display panel, a gate driving part, and a date driving part. The display panel includes a switching element disposed in association with a pixel, a main gate line connected to the switching element, and a sub gate line spaced apart from the main gate line and connected to the main gate line via a first connecting part. The gate driving part is configured to: provide the main gate line with a main gate signal, and provide the sub gate line with a sub gate signal. The sub gate signal includes a transmission difference from the main gate signal. The data driving part is configured to provide a data line with a data signal.

Abstract: A method of driving a display panel includes providing a switching element of a pixel of the display panel with a first polarity gate signal through a gate line connected to the switching element when the switching element receives a first polarity data signal having a first polarity with respect to a reference signal, and providing the switching element with a second polarity gate signal through the gate line when the switching element receives a second polarity data signal having a second polarity with respect to the reference signal through the data line.

Abstract: A display panel includes a gate line, a gate electrode, a planarization layer, a gate insulation layer, an active layer, a data line, a source electrode, a drain electrode, and a pixel electrode. The gate electrode extends from the gate line. The planarization layer covers the gate line and the gate electrode to have an opening exposing a portion of the gate electrode formed therethrough. The gate insulation layer covers a portion of the gate electrode exposed by the opening and the planarization layer. The active layer is formed on the gate insulation layer and corresponds to the gate electrode. The data line is formed. The source electrode extends from the data line to cover a portion of the opening. The drain electrode is spaced apart from the source electrode and covers a portion of the opening. The pixel electrode is connected to the drain electrode.

Abstract: A liquid crystal display includes first and second substrates, and a liquid crystal layer disposed therebetween. First and second gate lines are disposed on the first substrate. First and second data lines, and a power line are disposed on the first substrate. A first switching element is connected to the first gate line and the first data line, a second switching element is connected to the first gate line and the power line, a third switching element is connected to the second gate line and the second data line, a first pixel electrode is connected to the first switching element, a second pixel electrode is connected to the second switching element, a third pixel electrode is connected to the second switching element, and a fourth pixel electrode is connected to the third switching element, and a gate-on voltage can be simultaneously applied to the first and second gate lines.