Patents by Inventor Se-Hyung Jeon

Se-Hyung Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pixel clock generator, method of operating the same, and apparatuses including the pixel clock generator
    Patent number: 9203344
    Abstract: A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: December 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Jin Kim, Tae lk Kim, Se Hyung Jeon
  • PIXEL CLOCK GENERATOR, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE PIXEL CLOCK GENERATOR
    Publication number: 20140036150
    Abstract: A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 6, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Jin KIM, Tae Ik KIM, Se Hyung JEON
  • Duty correcting circuit, delay-locked loop circuit including the circuit, and method of correcting duty
    Patent number: 8456212
    Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Seok Kim, Do-Hyung Kim, Tae-Kwang Jang, Se-Hyung Jeon
  • DUTY CORRECTING CIRCUIT, DELAY-LOCKED LOOP CIRCUIT INCLUDING THE CIRCUIT, AND METHOD OF CORRECTING DUTY
    Publication number: 20110291726
    Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.
    Type: Application
    Filed: March 17, 2011
    Publication date: December 1, 2011
    Inventors: Woo-Seok KIM, Do-Hyung Kim, Tae-Kwang Jang, Se-Hyung Jeon