Patents by Inventor Se In KWON

Se In KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910224
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Publication number: 20200411323
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
  • Patent number: 10811260
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Publication number: 20190244820
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 8, 2019
    Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
  • Patent number: 10304684
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Publication number: 20180174845
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Application
    Filed: September 25, 2017
    Publication date: June 21, 2018
    Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
  • Patent number: 9530840
    Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventor: Se In Kwon
  • Publication number: 20160043172
    Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.
    Type: Application
    Filed: October 23, 2015
    Publication date: February 11, 2016
    Inventor: Se In KWON
  • Patent number: 9202865
    Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventor: Se In Kwon
  • Publication number: 20150108601
    Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.
    Type: Application
    Filed: April 1, 2014
    Publication date: April 23, 2015
    Applicant: SK hynix Inc.
    Inventor: Se In KWON
  • Patent number: 8865545
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se In Kwon
  • Publication number: 20140030883
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 30, 2014
    Applicant: SK HYNIX INC.
    Inventor: Se In KWON
  • Patent number: 8569817
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 29, 2013
    Assignee: Hynix Semiconductor Inc
    Inventor: Se In Kwon
  • Publication number: 20120043605
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a trench formed in the device isolation film and the active region, a gate electrode formed at the bottom of the trench, and a high dielectric material layer formed not only over the top of the gate electrode but also over a surface of the trench. As a result, although the gate electrode does not overlap with the junction region, the semiconductor device prevents channel resistance from being increased, resulting in an increase in semiconductor device characteristics.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 23, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Se In KWON, Hyun Jin LEE
  • Publication number: 20120012912
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 19, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Se In KWON