Patents by Inventor Se In KWON
Se In KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10910224Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.Type: GrantFiled: September 14, 2020Date of Patent: February 2, 2021Assignee: SK hynix Inc.Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
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Publication number: 20200411323Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
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Patent number: 10811260Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.Type: GrantFiled: April 12, 2019Date of Patent: October 20, 2020Assignee: SK hynix Inc.Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
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Publication number: 20190244820Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.Type: ApplicationFiled: April 12, 2019Publication date: August 8, 2019Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
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Patent number: 10304684Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.Type: GrantFiled: September 25, 2017Date of Patent: May 28, 2019Assignee: SK hynix Inc.Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
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Publication number: 20180174845Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.Type: ApplicationFiled: September 25, 2017Publication date: June 21, 2018Inventors: Tae-Su JANG, Jin-Chul PARK, Ji-Hwan PARK, Il-Sik JANG, Seong-Wan RYU, Se-In KWON, Jung-Ho SHIN, Dae-Jin HAM
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Patent number: 9530840Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.Type: GrantFiled: October 23, 2015Date of Patent: December 27, 2016Assignee: SK HYNIX INC.Inventor: Se In Kwon
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Publication number: 20160043172Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventor: Se In KWON
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Patent number: 9202865Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.Type: GrantFiled: April 1, 2014Date of Patent: December 1, 2015Assignee: SK Hynix Inc.Inventor: Se In Kwon
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Publication number: 20150108601Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.Type: ApplicationFiled: April 1, 2014Publication date: April 23, 2015Applicant: SK hynix Inc.Inventor: Se In KWON
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Patent number: 8865545Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.Type: GrantFiled: September 26, 2013Date of Patent: October 21, 2014Assignee: SK Hynix Inc.Inventor: Se In Kwon
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Publication number: 20140030883Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: SK HYNIX INC.Inventor: Se In KWON
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Patent number: 8569817Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.Type: GrantFiled: July 19, 2010Date of Patent: October 29, 2013Assignee: Hynix Semiconductor IncInventor: Se In Kwon
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Publication number: 20120043605Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a trench formed in the device isolation film and the active region, a gate electrode formed at the bottom of the trench, and a high dielectric material layer formed not only over the top of the gate electrode but also over a surface of the trench. As a result, although the gate electrode does not overlap with the junction region, the semiconductor device prevents channel resistance from being increased, resulting in an increase in semiconductor device characteristics.Type: ApplicationFiled: August 16, 2011Publication date: February 23, 2012Applicant: Hynix Semiconductor Inc.Inventors: Se In KWON, Hyun Jin LEE
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Publication number: 20120012912Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.Type: ApplicationFiled: July 19, 2010Publication date: January 19, 2012Applicant: Hynix Semiconductor Inc.Inventor: Se In KWON