Abstract: The present disclosure relates to an apparatus for obtaining a raw material which extracts a color raw material for cosmetics having a target color, wherein when a target color development value is input, raw material information is extracted using a genetic algorithm.

Abstract: A recombinant vector according to an embodiment is for genome editing without inserting a replicon into the plant genome in a T0 generation plant. The recombinant vector includes a geminivirus-based replicon between the sequence of LB (left border) and sequence of RB (right border) of Ti plasmid. A method of genome editing without inserting a replicon into the plant genome in a T0 generation plant according to an embodiment includes transforming a plant cell by inserting a foreign gene to the aforementioned recombinant vector.

Abstract: A vehicle height adjusting apparatus for adjusting a height of a vehicle body of a vehicle is provided. The vehicle height adjusting apparatus includes an electric motor provided with a stator and a rotor and formed to have a structure in which a central portion thereof is penetrated; a screw nut fixed to the rotor of the electric motor and provided with a threaded portion on an inner peripheral surface thereof; a screw shaft inserted into and coupled to the inner peripheral surface of the screw nut and provided with a corresponding threaded portion having a shape corresponding to the threaded portion of the screw nut on an outer peripheral surface thereof; a guide portion configured to guide a relative movement between the screw nut and the screw shaft in a longitudinal direction.

Abstract: An internal clock signal generator of a synchronous memory device is provided. The internal clock signal generator includes first and second inverting portions, a delay portion, first and second switching portions, and first and second logic portions also called input and output logic circuits, respectively. The first inverting portion inverts an external clock signal. The second inverting portion inverts an output signal of the first inverting portion. The delay portion delays an output signal of the second inverting portion. The first switching portion gates an output signal of the delay portion in response to a first control signal. The second switching portion gates the output signal of the second inverting portion in response to a second control signal. The first or input logic portion performs a logic operation with respect to signals input from an external source and outputting the first and second control signals.

Abstract: There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches.

Abstract: Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Abstract: A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2.sup.n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2.sup.

Abstract: There is provided in the present invention a signal generator which generates a bit line equalization signal and a signal generator which generates a sense amplifier equalization signal to control the bit line equalization circuit and the sense amplifier equalization circuit, respectively. The generated bit line equalization signal and sense amplifier equalization signal both have a voltage level that is at least about equal to, and preferably greater than, an external power supply voltage. The signals generated by these signal generators can thus be used by operating voltages which are much less than was previously possible.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device and a method for arranging a signal line therein which can realize a high bandwidth by embodying a chip architecture being comprised of a multi I/O line.

Abstract: A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2.sup.n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2.sup.