Abstract: A display device includes a first substrate, a first electrode above the first substrate, a pixel-defining film above the first electrode, and defining an emission area, a light-emitting layer above the first electrode and the pixel-defining film, a second electrode above the light-emitting layer, a thin-film encapsulation structure above the second electrode, and including an organic film defining an opening, and a color control layer above the thin-film encapsulation structure in the opening.

Abstract: A display device includes a pixel electrode including silver, a pixel-defining film on the pixel electrode and exposing the pixel electrode, a barrier layer on the pixel electrode and the pixel-defining film and including a low-resistance area and a high-resistance area which has a higher resistance than the low-resistance area, an emission layer on the barrier layer, and a common electrode on the emission layer. The low-resistance area of the barrier layer overlaps with the pixel electrode, and the high-resistance area of the barrier layer overlaps with the pixel-defining film.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of reading multi-bit data stored in a memory cell of a flash memory includes attempting to perform hard decision (HD) decoding on output data from the flash memory, and performing soft decision (SD) decoding on the output data when the HD decoding cannot be performed. The performing of the SD decoding includes: changing a maximum number of iterations according to a threshold voltage distribution of the memory cell; and performing the SD decoding based on the changed maximum number of iterations.

Abstract: A method of reading multi-bit data stored in a memory cell of a flash memory includes attempting to perform hard decision (HD) decoding on output data from the flash memory, and performing soft decision (SD) decoding on the output data when the HD decoding cannot be performed. The performing of the SD decoding includes: changing a maximum number of iterations according to a threshold voltage distribution of the memory cell; and performing the SD decoding based on the changed maximum number of iterations.

Abstract: A method of easily and inexpensively manufacturing an antenna for an RFID tag by forming the antenna using magnets of a pattern corresponding to a shape of the antenna is provided. One example method includes a) placing a substrate above a level of a fluid containing a conductive substance, b) placing a magnet (e.g., an electromagnet including an electrode) formed in a shape of an antenna pattern above a surface of the substrate, and adhering the conductive substance to a bottom of the substrate in the shape of the antenna pattern by a magnetic force, and c) fixing the conductive substance adhered to the bottom of the substrate.

Abstract: An ultra high frequency (UHF) radio frequency identification (RFID) tag and a method of manufacturing the tag are provided. The tag includes a substrate, a chip attached to the substrate and having a plurality of bumps for connecting a circuit formed therein with an external, and at least one UHF antenna extended in a longitudinal direction and responding to ultra high frequency transferred from the external, at least one end of the UHF antenna connected to the bump, and one portion of the antenna fixed to the substrate.

Abstract: A method of easily and inexpensively manufacturing an antenna for an RFID tag by forming the antenna using magnets of a pattern corresponding to a shape of the antenna is provided. The method includes a) placing a substrate above a level of a fluid containing a conductive substance, b) placing an electrode formed in a shape of an antenna pattern above a surface of the substrate, and applying a current to the electrode, to adhere the conductive substance to a bottom of the substrate in the shape of the antenna pattern by an electromagnetic force, and c) fixing the conductive substance adhered to the bottom of the substrate.