Abstract: A computing system is configured to access intermediate outputs of a neural network by augmenting a data flow graph generated for the neural network. The data flow graph includes a plurality of nodes interconnected by connections, each node representing an operation to be executed by the neural network. To access the intermediate output, the data flow graph is augmented by inserting a node representing an operation that saves the output of a node which produces the intermediate output. The node representing the save operation is inserted while maintaining all existing nodes and connections in the data flow graph, thereby preserving the behavior of the data flow graph. The augmenting can be performed using a compiler that generates the data flow graph from program code.

Abstract: Apparatuses, systems, and techniques to modify performance of a neural network. In at least one embodiment, performance of one or more neural networks is modified based, at least in part, on a user-provided description of at least portions of the one or more neural networks.

Abstract: Provided are integrated circuits and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation. The tensor may be decomposed into blocks of data elements having dimensions consistent with the dimensions of a systolic array. An identity multiplication may be performed on each block of data elements loaded into a systolic array and the multiplication products summed in column partitions of a results buffer. The data elements in the column partitions of results buffer can then be mapped to row partitions of a buffer memory for further processing.

Abstract: Techniques are disclosed for debugging a neural network execution on a target processor. A reference processor may generate a plurality of first reference tensors for the neural network. The neural network may be repeatedly reduced to produce a plurality of lengths. For each of the lengths, a compiler converts the neural network into first machine instructions, the target processor executes the first machine instructions to generate a first device tensor, and the debugger program determines whether the first device tensor matches a first reference tensor. A shortest length is identified for which the first device tensor does not match the first reference tensor. Tensor output is enabled for a lower-level intermediate representation of the shortest neural network, and the neural network is converted into second machine instructions, which are executed by the target processor to generate a second device tensor.

Abstract: Provided are integrated circuits and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation. The tensor may be decomposed into blocks of data elements having dimensions consistent with the dimensions of a systolic array. An identity multiplication may be performed on each block of data elements loaded into a systolic array and the multiplication products summed in column partitions of a results buffer. The data elements in the column partitions of results buffer can then be mapped to row partitions of a buffer memory for further processing.

Abstract: Provided are systems and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation. The tensor may be decomposed into blocks of data elements having dimensions consistent with the dimensions of a systolic array. An identity multiplication may be performed on each block of data elements loaded into a systolic array and the multiplication products summed in column partitions of a results buffer. The data elements in the column partitions of results buffer can then be mapped to row partitions of a buffer memory for further processing.

Abstract: Techniques are disclosed for debugging a neural network execution on a target processor. A reference processor may generate a plurality of first reference tensors for the neural network. The neural network may be repeatedly reduced to produce a plurality of lengths. For each of the lengths, a compiler converts the neural network into first machine instructions, the target processor executes the first machine instructions to generate a first device tensor, and the debugger program determines whether the first device tensor matches a first reference tensor. A shortest length is identified for which the first device tensor does not match the first reference tensor. Tensor output is enabled for a lower-level intermediate representation of the shortest neural network, and the neural network is converted into second machine instructions, which are executed by the target processor to generate a second device tensor.

Abstract: Provided are systems and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation. The tensor may be decomposed into blocks of data elements having dimensions consistent with the dimensions of a systolic array. An identity multiplication may be performed on each block of data elements loaded into a systolic array and the multiplication products summed in column partitions of a results buffer. The data elements in the column partitions of results buffer can then be mapped to row partitions of a buffer memory for further processing.

Abstract: A method for configuring a Wireless Local Area Network (WLAN) within a Wireless Metropolitan Area Network (WMAN) and a wireless communication system supporting the same are provided. A dual-mode terminal is used as a relay for relaying between the WMAN and the WLAN and the relay divides a total service period into a WMAN period and a WLAN period. For the WMAN period, the relay accesses the WMAN and implements a WMAN service and for the WLAN period, it accesses the WLAN and implements a WLAN service.

Abstract: This disclosure describes techniques for allocating registers in a computing system that supports vector physical registers. The techniques for allocating registers may allocate physical registers to vector virtual registers based on priority information that is indicative of a relative importance of allocating respective vector virtual registers as vectors rather than scalars. The techniques for allocating registers may involve allocating physical registers to the vector virtual registers in an order that is determined based on the priority information.

Abstract: The present invention relates to a semiconductor device capable of emitting light upon application of voltage and a method for manufacturing the same, and more particularly to a semiconductor device having a polygonal or circular columnar shape and a method for manufacturing the same. The semiconductor device of the present invention comprises a plurality of semiconductor structures and a connecting support layer that supports the plurality of the semiconductor structures, wherein each of the plurality of the semiconductor structures comprises a P-type first semiconductor layer, an N-type second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, and forms a column having a polygonal or circular shape.

Abstract: This disclosure describes techniques for allocating registers in a computing system that supports vector physical registers. The techniques for allocating registers may allocate physical registers to vector virtual registers based on priority information that is indicative of a relative importance of allocating respective vector virtual registers as vectors rather than scalars. The techniques for allocating registers may involve allocating physical registers to the vector virtual registers in an order that is determined based on the priority information.

Abstract: The present invention relates to a semiconductor device, a manufacturing method thereof. More specifically, this invention is related to a chemical etching method in semiconductor device separation process without using dicing or scribing. According to an example of the invention, a method for manufacturing a semiconductor device, the method comprising: forming a light emitting semiconductor device layer that emits light by current injection; and forming at least one metal layer with etch barrier plated thereon on the semiconductor device layer, wherein the at least one metal layer provides mechanical support to the semiconductor device, wherein the etch barrier is plated on the at least one metal layer in a direction that the etch barrier can prevent side wall under-cut when the street lines are separated by wet chemical etching.

Abstract: A method for configuring a Wireless Local Area Network (WLAN) within a Wireless Metropolitan Area Network (WMAN) and a wireless communication system supporting the same are provided. A dual-mode terminal is used as a relay for relaying between the WMAN and the WLAN and the relay divides a total service period into a WMAN period and a WLAN period. For the WMAN period, the relay accesses the WMAN and implements a WMAN service and for the WLAN period, it accesses the WLAN and implements a WLAN service.

Abstract: A method for configuring a Wireless Local Area Network (WLAN) within a Wireless Metropolitan Area Network (WMAN) and a wireless communication system supporting the same are provided. A dual-mode terminal is used as a relay for relaying between the WMAN and the WLAN and the relay divides a total service period into a WMAN period and a WLAN period. For the WMAN period, the relay accesses the WMAN and implements a WMAN service and for the WLAN period, it accesses the WLAN and implements a WLAN service.

Abstract: The present invention relates to a semiconductor device capable of emitting light upon application of voltage and a method for manufacturing the same, and more particularly to a semiconductor device having a polygonal or circular columnar shape and a method for manufacturing the same. The semiconductor device of the present invention comprises a plurality of semiconductor structures and a connecting support layer that supports the plurality of the semiconductor structures, wherein each of the plurality of the semiconductor structures comprises a P-type first semiconductor layer, an N-type second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, and forms a column having a polygonal or circular shape.

Abstract: A method, medium, and apparatus controlling a handover between different network types, including the operations of transmitting a message requesting a transmission bandwidth change, so as to have a transmission bandwidth supported by a new network after movement of the mobile terminal, from the mobile terminal to the server after performing the handover, changing the transmission bandwidth of the server to be supported by the new network based on the transmitted message of requesting the bandwidth change, transmitting a message acknowledging the changed transmission bandwidth from the server to the router, and transceiving data through a new data transmission tunnel between the router and a new access point within the new based on the message acknowledging the changed transmission bandwidth. Accordingly, loss of data packets occurring when a handover is performed may be effectively prevented.

Abstract: Provided is a method and apparatus for decreasing a handover latency time using a context exchange between a mobile terminal (MT) and a Media Independent Handover Server (MIHS). The method used by the MT for decreasing handover latency between a first network and a second network includes when a handover is performed from the first network to the second network, transmitting to the MIHS information required for first network communication as context; and when a handover is performed from the second network to the first network, receiving from the MIHS first network access information comprising the context through the currently used second network. Accordingly, the MT can reduce a Vertical Handover (VHO) latency time and simultaneously consume almost the same power as a single mode terminal.

Abstract: A method, medium, and apparatus controlling a handover between different network types, including the operations of transmitting a message requesting a transmission bandwidth change, so as to have a transmission bandwidth supported by a new network after movement of the mobile terminal, from the mobile terminal to the server after performing the handover, changing the transmission bandwidth of the server to be supported by the new network based on the transmitted message of requesting the bandwidth change, transmitting a message acknowledging the changed transmission bandwidth from the server to the router, and transceiving data through a new data transmission tunnel between the router and a new access point within the new based on the message acknowledging the changed transmission bandwidth. Accordingly, loss of data packets occurring when a handover is performed may be effectively prevented.

Abstract: A method, medium, and apparatus controlling a handover between different network types, including the operations of transmitting a message requesting a transmission bandwidth change, so as to have a transmission bandwidth supported by a new network after movement of the mobile terminal, from the mobile terminal to the server after performing the handover, changing the transmission bandwidth of the server to be supported by the new network based on the transmitted message of requesting the bandwidth change, transmitting a message acknowledging the changed transmission bandwidth from the server to the router, and transceiving data through a new data transmission tunnel between the router and a new access point within the new based on the message acknowledging the changed transmission bandwidth. Accordingly, loss of data packets occurring when a handover is performed may be effectively prevented.