Abstract: A junction passage control system based on a location of an OHT using a power line communication, includes: an OHT controller mounted on an OHT which moves along tracks; and a central controller that is installed in a junction section of the tracks and controls junction passing of a plurality of OHTs, wherein power lines are laid on the tracks in a zone from a start point of the junction section to an end point of the junction section, and the central controller and the OHT controller transmit and receive data for a junction passage control through power line communication to and from each other.

Abstract: A battery cell includes: an electrode assembly; a pouch case accommodating the electrode assembly therein; and an electrode lead including an outer lead protruding to an outside of the pouch case and an inner lead disposed between the outer lead and the electrode assembly, accommodated in the pouch case, bent plural times in a direction in which it connects the electrode assembly and the outer lead to each other, and cut by expansion force of the pouch case.

Abstract: A battery cell includes: an electrode assembly; a pouch case accommodating the electrode assembly therein; and an electrode lead including an outer lead protruding to an outside of the pouch case and an inner lead disposed between the outer lead and the electrode assembly, accommodated in the pouch case, bent plural times in a direction in which it connects the electrode assembly and the outer lead to each other, and cut by expansion force of the pouch case.

Abstract: A sauna apparatus for a half-body bath including a body having a concave structure surrounded with a bottom surface located horizontally on the ground and at least three surfaces connected to the bottom surface. The sauna apparatus also includes a first heating part and a seat disposed at the inside thereof. The sauna apparatus further includes a cover connected on top of the body that is movable-up and down to open and close the interior of the body. The sauna apparatus also includes a second heating part in the cover and shock absorbers to connect the body and the cover with each other. In addition, the sauna apparatus includes a seat driving part to move the seat in an advancing or opposite direction.

Abstract: The present invention relates to a sauna apparatus for a half-body bath including: a body having a concave structure surrounded with a bottom surface located horizontally on the ground and at least three surfaces connected to the bottom surface and comprising a first heating part and a seat disposed at the inside thereof; a cover connectedly placed on top of the body in such a manner as to move up and down by a force applied thereto to open and close the interior of the body and having a second heating part disposed at the inside thereof; shock absorbers adapted to connect the body and the cover with each other; and a seat driving part adapted to generate power according to input signals applied thereto to move the seat in an advancing direction or in an opposite direction to the advancing direction.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: Transistors and electronic apparatuses including the same are provided, the transistors include a channel layer on a substrate. The channel layer includes a zinc (Zn)-containing oxide. The transistors include a source and a drain, respectively, contacting opposing ends of the channel layer, a gate corresponding to the channel layer, and a gate insulating layer insulating the channel layer from the gate. The channel layer has a first surface adjacent to the substrate, a second surface facing the first surface, and a channel layer-protection portion on the second surface. The channel layer-protection portion includes a fluoride material.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure includes: (a) a first process of bonding a device wafer and a handling wafer; (b) a second process of thinning a back side of an Si substrate which is formed on the device wafer, after the first process; (c) a third process of forming an anti-reflective layer and a PMD (preferential metal deposition) dielectric layer, after the second process; (d) a fourth process of forming vias on back sides of super contacts which are formed on the Si substrate, after the third process; and (e) a fifth process of forming a pad, after the fourth process.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: Transistors and electronic apparatuses including the same are provided, the transistors include a channel layer on a substrate. The channel layer includes a zinc (Zn)-containing oxide. The transistors include a source and a drain, respectively, contacting opposing ends of the channel layer, a gate corresponding to the channel layer, and a gate insulating layer insulating the channel layer from the gate. The channel layer has a first surface adjacent to the substrate, a second surface facing the first surface, and a channel layer-protection portion on the second surface. The channel layer-protection portion includes a fluoride material.

Abstract: An image sensor for reducing crosstalk includes anti-reflection films which are formed between a plurality of metal wire lines of the lowest metal wiring layer and a semiconductor substrate and between one of the metal wiring layers and another metal wiring layer. The image sensor having the anti-reflection films according to the present invention can reduce color crosstalk and noises in comparison with a conventional image sensor by using the anti-reflection films formed above the surroundings of the photodiodes.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: The present invention provides a pixel array having a three-dimensional structure and an image sensor having the pixel array. The pixel array has a three-dimensional structure in which a photodiode, a transfer transistor, a reset transistor, a convert transistor, and a select transistor are divided and formed on a first wafer and a second wafer, chips on the first and second wafers are connected in a vertical direction after die-sorting the chips.