Patents by Inventor Se-Keun Park

Se-Keun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240067668
    Abstract: The present invention relates to a heteroaryl derivative compound and a use thereof. Since the heteroaryl derivative of the present invention exhibits excellent inhibitory activity against EGFR, the heteroaryl derivative can be usefully used as a therapeutic agent for EGFR-associated diseases.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 29, 2024
    Inventors: Yi Kyung Ko, Ah Reum Han, Jin Hee Park, Yeong Deok Lee, Hye Rim Im, Kyun Eun Kim, Dong Keun Hwang, Su Been Nam, Myung Hoe Heo, Se Rin Cho, Eun Hwa Ko, Sung Hwan Kim, Hwan Geun Choi
  • Patent number: 11189570
    Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-a Kim, Yong-kwan Kim, Se-keun Park, Ho-in Ryu
  • Patent number: 11177264
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 16, 2021
    Inventors: Jae-hyeon Jeon, Se-keun Park, Dong-sik Park, Seok-ho Shin
  • Patent number: 11152374
    Abstract: A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-A Kim, Yong-Kwan Kim, Se-Keun Park, Jung-Woo Song, Joo-Young Lee
  • Patent number: 10797056
    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-A Kim, Yong-Kwan Kim, Se-Keun Park, Joo-Young Lee, Cha-Won Koh, Yeong-Cheol Lee
  • Publication number: 20200194374
    Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.
    Type: Application
    Filed: November 5, 2019
    Publication date: June 18, 2020
    Inventors: Jin-a KIM, Yong-kwan KIM, Se-keun PARK, Ho-in RYU
  • Publication number: 20200168611
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.
    Type: Application
    Filed: September 10, 2019
    Publication date: May 28, 2020
    Inventors: Jae-hyeon Jeon, Se-keun Park, Dong-sik Park, Seok-ho Shin
  • Publication number: 20200161308
    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Applicant: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Inventors: Jin-A KIM, Yong-Kwan Kim, Se-Keun Park, Joo-Young Lee, Cha-Won Koh, Yeong-Cheol Lee
  • Patent number: 10586798
    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, word lines, a doped junction, bit line structures, and buried contacts. The substrate has active regions. The word lines extend across the active regions. The doped junction has impurities and is arranged at the active regions, and includes first junctions and second junctions, each first junction arranged at a central portion of one of the active regions and each second junction arranged at an end portion of another one of the active regions, a buried semiconductor layer being included in each second junction. The bit line structures contact with a respective one of the first junctions. The buried contacts are arranged in a matrix shape, each contacting with a respective one of the second junctions and the included buried semiconductor layer and simultaneously contacting with a charge storage for storing data.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-A Kim, Yong-Kwan Kim, Se-Keun Park, Joo-Young Lee, Cha-Won Koh, Yeong-Cheol Lee
  • Publication number: 20190206872
    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, word lines, a doped junction, bit line structures, and buried contacts. The substrate has active regions. The word lines extend across the active regions. The doped junction has impurities and is arranged at the active regions, and includes first junctions and second junctions, each first junction arranged at a central portion of one of the active regions and each second junction arranged at an end portion of another one of the active regions, a buried semiconductor layer being included in each second junction. The bit line structures contact with a respective one of the first junctions. The buried contacts are arranged in a matrix shape, each contacting with a respective one of the second junctions and the included buried semiconductor layer and simultaneously contacting with a charge storage for storing data.
    Type: Application
    Filed: October 25, 2018
    Publication date: July 4, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-A KIM, Yong-Kwan KIM, Se-Keun PARK, Joo-Young LEE, Cha-Won KOH, Yeong-Cheol LEE
  • Publication number: 20190206873
    Abstract: A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.
    Type: Application
    Filed: October 26, 2018
    Publication date: July 4, 2019
    Inventors: Jin-A KIM, Yong-Kwan KIM, Se-Keun PARK, Jung-Woo SONG, Joo-Young LEE
  • Patent number: 9224619
    Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seol-Min Yi, Dae-Hyun Moon, Joon-Seok Moon, Se-Keun Park, Hyeoung-Won Seo
  • Publication number: 20150221742
    Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.
    Type: Application
    Filed: September 30, 2014
    Publication date: August 6, 2015
    Inventors: Seol-Min YI, Dae-Hyun MOON, Joon-Seok MOON, Se-Keun PARK, Hyeoung-Won SEO
  • Publication number: 20140048856
    Abstract: A semiconductor device includes an active area defined by a device isolation layer and including a plurality of source/drain regions, a gate structure disposed on the active area and extending in a first direction, a stress layer contacting a side surface of each of the plurality of source/drain regions and a plurality of source/drain contacts disposed in the active area and connected to the plurality of source/drain regions.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JAE-JOON SONG, Se-Keun Park
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 8207573
    Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Se-Keun Park
  • Patent number: 8198163
    Abstract: A method of fabricating a semiconductor device including forming a plurality of gate structures on a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, forming a dielectric layer on the semiconductor substrate having the gate structures, forming contact holes by etching the dielectric layer to expose parts of the impurity regions at sides of the gate structures, directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and forming conductive plugs in the contact holes.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Park, Se-keun Park
  • Publication number: 20110163394
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Application
    Filed: June 10, 2010
    Publication date: July 7, 2011
    Inventors: Joo-Sung Park, Se-Keun Park
  • Publication number: 20100124808
    Abstract: A method of fabricating a semiconductor device including forming a plurality of gate structures on a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, forming a dielectric layer on the semiconductor substrate having the gate structures, forming contact holes by etching the dielectric layer to expose parts of the impurity regions at sides of the gate structures, directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and forming conductive plugs in the contact holes.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 20, 2010
    Inventors: Joo-sung Park, Se-keun Park
  • Publication number: 20090250749
    Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.
    Type: Application
    Filed: June 12, 2009
    Publication date: October 8, 2009
    Inventor: Se-Keun Park