Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.

Abstract: An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a memory block, a driving circuit performing a program operation on memory cells and a voltage detector generating a detection signal when an external power supply voltage is reduced to less than a reference voltage level. The driving circuit discharges a voltage applied to a drain selection line during the program operation in response to the detection signal.

Abstract: An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a memory block, a driving circuit performing a program operation on memory cells and a voltage detector generating a detection signal when an external power supply voltage is reduced to less than a reference voltage level. The driving circuit discharges a voltage applied to a drain selection line during the program operation in response to the detection signal.

Abstract: A method for fabricating a semiconductor memory device includes forming a channel region in a substrate, selectively etching the substrate to form a first trench, performing an impurity ion implantation process on the channel region, and etching a lower portion of the first trench to form a second trench.

Abstract: Provided is a method of manufacturing a flash memory device. In accordance with the present invention, an undoped polysilicon layer is formed over a semiconductor substrate where a floating gate and a dielectric layer are formed. By performing N2 plasma process with respect to the undoped polysilicon layer, a heavily doped polysilicon layer is formed to form a control gate. Due to N2 plasma process, a nitrogen layer is formed at the interfaces between the dielectric layer and the undoped polysilicon layer. As a result, during a re-oxidization process, it is possible to prevent a thickness of the dielectric layer from being increased by reducing diffusion speed phosphorous and oxygen. Additionally, phosphorous of the heavily doped polysilicon layer is diffused into the undoped polysilicon layer in a subsequent process, thereby increasing a phosphorous concentration of the undoped polysilicon layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of memory cells and transistors over a substrate, forming a first stopping layer having tensile stress over the plurality of memory cells and transistors, forming a first insulation layer over the substrate and the first stopping layer, and forming a second stopping layer having compression stress over the first insulation layer.

Abstract: In the method for fabricating an element isolating film of a semiconductor device, a trench is formed in the semiconductor substrate, and a side wall spacer is formed at a side wall of the trench. A silicon layer is formed on a bottom surface of the trench, and a groove portion is formed in the bottom surface of the trench by removing the side wall spacer. An element isolating film is then formed by filling an oxide film in the trench.

Abstract: In the method for fabricating an element isolating film of a semiconductor device, a trench is formed in the semiconductor substrate, and a side wall spacer is formed at a side wall of the trench. A silicon layer is formed on a bottom surface of the trench, and a groove portion is formed in the bottom surface of the trench by removing the side wall spacer. An element isolating film is then formed by filling an oxide film in the trench.