Patents by Inventor Se-min Yang

Se-min Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379406
    Abstract: A semiconductor device is disclosed. The semiconductor memory device comprises a substrate including an active region, an element isolation film disposed in the substrate and that defines the active region, a recess which is disposed in the active region and extends in a first direction, and a gate structure extending in a second direction, on the active region, wherein the gate structure includes a gate insulating film, a gate stack pattern, and a gate capping pattern which are sequentially stacked, wherein the gate insulating film extends along an upper face of the active region, and a part of the gate insulating film fills the recess, and wherein a height from a lower face of the substrate to a bottom face of the element isolation film is less than a height from the lower face of the substrate to a bottom face of the recess.
    Type: Application
    Filed: December 22, 2023
    Publication date: November 14, 2024
    Inventors: Hee Sung LEE, Tae Sung KANG, Se Min YANG, Kyo-Suk CHAE, Seung Ho HONG, Beom Yong HWANG
  • Publication number: 20240352199
    Abstract: The present invention provides a method for preparing a swellable polymer to which an object is fixed. The preparation method of the present invention comprises a step of absorbing a solution of an object, which is dissolved or dispersed in a solvent with affinity for a swellable polymer, into a dried swellable polymer comprising a linker having a functional group that can bind to the object. Unlike a conventional preparation method in which an object is fixed before a swellable polymer is cross-linked, a method using a swellable polymer so as to fix an object after a polymer is cross-linked is used, and thus an object can be more rapidly fixed with efficiency higher than that of a conventional technique.
    Type: Application
    Filed: August 19, 2022
    Publication date: October 24, 2024
    Applicant: PUSAN NATIONAL UNIVERSITY INDUSTRY-UNIVERSITY COOPERATION FOUNDATION
    Inventors: Seung Yun YANG, Sodam KIM, Jian LEE, Se Min KIM
  • Publication number: 20240247780
    Abstract: The present invention provides a light source apparatus and method for integrating diffused light with high efficiency using a collimating including an axicon lens, collimating it, tuning the wavelength of desired light, and passing it.
    Type: Application
    Filed: January 24, 2023
    Publication date: July 25, 2024
    Applicant: IISM INC.
    Inventors: IL SEUNG YANG, YUN MI BAE, YU SIC KIM, SUNG YUN CHO, KWAN KYU LEE, JAE KEUN CHOI, YOUN JIN KIM, CHANG HYUN BAE, SUNG DONG KIM, JONG MIN PARK, YUN JI LEE, SE MIN PARK, HUENG KHON KIM
  • Patent number: 11670537
    Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
  • Publication number: 20230085469
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, device isolation films defining an active region in the substrate, the active region defined in the substrate by the device isolation films, a gate pattern formed in the active region, and source/drain regions on both sides of the gate pattern, in the active region, the source/drain regions include first parts, which are doped with carbon monoxide (CO) ions and are recrystallized.
    Type: Application
    Filed: May 31, 2022
    Publication date: March 16, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Se Min YANG, Byung Jae KANG, Jong Keum LEE, Hee Sung LEE
  • Publication number: 20210183689
    Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 17, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
  • Patent number: 10930544
    Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
  • Publication number: 20200243375
    Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.
    Type: Application
    Filed: August 14, 2019
    Publication date: July 30, 2020
    Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee