Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.

Abstract: A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.

Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.

Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.

Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.

Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.

Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.

Abstract: A method of fabricating a semiconductor device, the method including forming a buffer oxide layer in a first region and a second region of a semiconductor substrate; forming a plurality of first preliminary mask patterns on the buffer oxide layer in the first region; forming a plurality of second preliminary mask patterns between every two adjacent first preliminary mask patterns from among the plurality of first preliminary mask patterns, respectively; forming a plurality of first mask patterns and a plurality of second mask patterns by trimming the plurality of first preliminary mask patterns and the plurality of second preliminary mask patterns; forming a plurality of first active region mask patterns for exposing the semiconductor substrate; defining a plurality of active regions in the semiconductor substrate by forming a trench including a plurality of first trench spaces having same width as the first space and a plurality of second trench spaces under the second space in the first region; and forming

Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.

Abstract: A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars.

Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.

Abstract: A method of fabricating a semiconductor device, the method including forming a buffer oxide layer in a first region and a second region of a semiconductor substrate; forming a plurality of first preliminary mask patterns on the buffer oxide layer in the first region; forming a plurality of second preliminary mask patterns between every two adjacent first preliminary mask patterns from among the plurality of first preliminary mask patterns, respectively; forming a plurality of first mask patterns and a plurality of second mask patterns by trimming the plurality of first preliminary mask patterns and the plurality of second preliminary mask patterns; forming a plurality of first active region mask patterns for exposing the semiconductor substrate; defining a plurality of active regions in the semiconductor substrate by forming a trench including a plurality of first trench spaces having same width as the first space and a plurality of second trench spaces under the second space in the first region; and forming

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.

Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.

Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.

Abstract: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.