Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.