Patents by Inventor Se Yeul Bae
Se Yeul Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7977770Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.Type: GrantFiled: June 11, 2008Date of Patent: July 12, 2011Assignee: Dongbu Electronics Co., Ltd.Inventor: Se-Yeul Bae
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Patent number: 7960839Abstract: An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.Type: GrantFiled: April 20, 2007Date of Patent: June 14, 2011Assignee: Dongbu Electronics Co., Ltd.Inventor: Se-Yeul Bae
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Patent number: 7745266Abstract: The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.Type: GrantFiled: December 28, 2005Date of Patent: June 29, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Se-Yeul Bae
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Patent number: 7648870Abstract: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is deposited over the first conductive layer. A second conductive layer is buried in the interlayer dielectric layer by a dual damascene process to simultaneously form an interconnection and a fuse. The resultant structure is coated with a passivation layer. The fuse is cut to form a severed portion. A selective metal layer is deposited over the severed portion.Type: GrantFiled: December 26, 2006Date of Patent: January 19, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Se Yeul Bae
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Patent number: 7618887Abstract: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.Type: GrantFiled: December 16, 2005Date of Patent: November 17, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Se-Yeul Bae
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Publication number: 20080246156Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.Type: ApplicationFiled: June 11, 2008Publication date: October 9, 2008Inventor: Se-Yeul Bae
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Patent number: 7399698Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.Type: GrantFiled: December 30, 2005Date of Patent: July 15, 2008Assignee: Dongbu Electronics Co., LtdInventor: Se-Yeul Bae
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Publication number: 20070194448Abstract: An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.Type: ApplicationFiled: April 20, 2007Publication date: August 23, 2007Inventor: Se-Yeul Bae
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Publication number: 20070161232Abstract: A method for forming metal interconnections in a semiconductor damascene process, in which a selective deposition of an etch stop layer formed above a lower metal interconnection by the damascene process prevents an etch attack against the lower metal interconnection. The method includes forming a first conductive layer over a semiconductor substrate.Type: ApplicationFiled: December 26, 2006Publication date: July 12, 2007Inventor: Se Yeul Bae
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Publication number: 20070148956Abstract: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is deposited over the first conductive layer. A second conductive layer is buried in the interlayer dielectric layer by a dual damascene process to simultaneously form an interconnection and a fuse. The resultant structure is coated with a passivation layer. The fuse is cut to form a severed portion. A selective metal layer is deposited over the severed portion.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Se Yeul Bae
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Patent number: 7223686Abstract: An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.Type: GrantFiled: December 30, 2004Date of Patent: May 29, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Se-Yeul Bae
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Publication number: 20060163700Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.Type: ApplicationFiled: December 30, 2005Publication date: July 27, 2006Inventor: Se-Yeul Bae
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Publication number: 20060138589Abstract: The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.Type: ApplicationFiled: December 28, 2005Publication date: June 29, 2006Inventor: Se-Yeul Bae
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Publication number: 20060131756Abstract: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.Type: ApplicationFiled: December 16, 2005Publication date: June 22, 2006Applicant: DongbuAnam Semiconductor Inc.Inventor: Se-Yeul Bae
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Publication number: 20050140020Abstract: An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.Type: ApplicationFiled: December 30, 2004Publication date: June 30, 2005Inventor: Se-Yeul Bae
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Patent number: 6897136Abstract: A method for forming a fuse in a semiconductor device comprising: forming a second insulating layer on a first insulating layer; etching the second insulating layer to form a trench; depositing a first metal layer on the trench and the second insulating layer; performing a chemical-mechanical polishing (CMP) process on the first metal layer to form the first metal wiring; forming a third insulating layer on the first metal wiring and the second insulating layer; etching the third insulating layer to form a second trench; depositing a barrier layer and a second metal layer on the second trench and the third insulating layer, and performing a CMP process on the barrier layer and the third insulating layer to form the second metal wiring; depositing a buffer layer on the second metal wiring and the third insulating layer; forming a passivation layer on the buffer layer; and etching the passivation layer.Type: GrantFiled: December 23, 2002Date of Patent: May 24, 2005Assignee: Dongbu Electronics Co., Ltd.Inventor: Se Yeul Bae
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Publication number: 20040132280Abstract: The present invention relates to a method of forming metal wiring in a semiconductor device, and the method includes forming a bottom metal pattern on a semiconductor substrate, forming an insulating layer on the semiconductor substrate including the bottom metal pattern, forming a first photoresist pattern for forming vial hole on the insulating layer, forming an unfinished via hole by removing the insulating layer selectively for a prescribed thickness using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second photoresist pattern for forming damascene pattern on the insulating layer around the unfinished via hole, forming a damascene pattern by removing the insulating layer selectively using the second photoresist pattern as a mask, removing the second photoresist pattern, and forming a metal wiring via damascene contact by filling metal in the damascene pattern.Type: ApplicationFiled: July 25, 2003Publication date: July 8, 2004Applicant: Dongbu Electronics Co. Ltd.Inventor: Se-Yeul Bae
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Publication number: 20030119293Abstract: A method for forming a fuse in a semiconductor device comprising: forming a second insulating layer on a first insulating layer; etching the second insulating layer to form a trench; depositing a first metal layer on the trench and the second insulating layer; performing a chemical-mechanical polishing (CMP) process on the first metal layer to form the first metal wiring; forming a third insulating layer on the first metal wiring and the second insulating layer; etching the third insulating layer to form a second trench; depositing a barrier layer and a second metal layer on the second trench and the third insulating layer, and performing a CMP process on the barrier layer and the third insulating layer to form the second metal wiring; depositing a buffer layer on the second metal wiring and the third insulating layer; forming a passivation layer on the buffer layer; and etching the passivation layer.Type: ApplicationFiled: December 23, 2002Publication date: June 26, 2003Inventor: Se Yeul Bae