Abstract: Disclosed is a display module including a transparent display panel and a frame to fix a side of the transparent display panel, wherein the frame has a communication unit to receive data from the outside, a controller to process the received data and to output a drive command corresponding to the processed data and a display drive unit to drive the transparent display panel in response to the drive command from the controller. A display system includes a system body and a display module detachably mounted in the system body.

Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.

Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.

Abstract: Disclosed is a display module including a transparent display panel and a frame to fix a side of the transparent display panel, wherein the frame has a communication unit to receive data from the outside, a controller to process the received data and to output a drive command corresponding to the processed data and a display drive unit to drive the transparent display panel in response to the drive command from the controller. A display system includes a system body and a display module detachably mounted in the system body.

Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.

Abstract: Disclosed is a display module including a transparent display panel and a frame to fix a side of the transparent display panel, wherein the frame has a communication unit to receive data from the outside, a controller to process the received data and to output a drive command corresponding to the processed data and a display drive unit to drive the transparent display panel in response to the drive command from the controller. A display system includes a system body and a display module detachably mounted in the system body.

Abstract: A thin film deposition apparatus and a method of maintaining the same are disclosed. In one embodiment, a thin film deposition apparatus includes: a chamber including a removable chamber cover; one or more reactors housed in the chamber; a chamber cover lifting device connected to the chamber cover. The chamber cover lifting device is configured to move the chamber cover vertically between a lower position and an upper position. The apparatus further includes a level sensing device configured to detect whether the chamber cover is level, and a level maintaining device configured to adjust the chamber cover if the chamber cover is not level. This configuration maintains the chamber cover to be level as a condition for further vertical movement of the chamber cover.

Abstract: Disclosed is a display module including a transparent display panel and a frame to fix a side of the transparent display panel, wherein the frame has a communication unit to receive data from the outside, a controller to process the received data and to output a drive command corresponding to the processed data and a display drive unit to drive the transparent display panel in response to the drive command from the controller. A display system includes a system body and a display module detachably mounted in the system body.

Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.

Abstract: A thin film deposition apparatus and a method of maintaining the same are disclosed. In one embodiment, a thin film deposition apparatus includes: a chamber including a removable chamber cover; one or more reactors housed in the chamber; a chamber cover lifting device connected to the chamber cover. The chamber cover lifting device is configured to move the chamber cover vertically between a lower position and an upper position. The apparatus further includes a level sensing device configured to detect whether the chamber cover is level, and a level maintaining device configured to adjust the chamber cover if the chamber cover is not level. This configuration maintains the chamber cover to be level as a condition for further vertical movement of the chamber cover.

Abstract: A data interfacing apparatus for interfacing a frame memory with upper and lower address electrode drivers in an alternating current type plasma display panel system is disclosed. The data interfacing apparatus includes a pair of provisional storing sections for provisionally storing RGB data supplied from the frame memory and a shift signal generator for generating a clock signal to provide the clock signal to the respective provisional storing sections. Each of the provisional storing sections includes N shift registers consisting of M delayed flip-flops. Respective input terminals of the shift registers are connected to N output terminals of the frame memory one-to-one. The respective shift registers shift M times the RGB data, which is transferred to the respective input terminals by one bit from the frame memory, and provisionally latch N×M bits RGB data in response to a clock signal.

Abstract: A circuit for driving address electrodes of a plasma display panel system is disclosed. A data interfacing section outputs red, green and blue data arranged on 12 columns×107 rows to an address electrode driving IC. The address electrode driving IC has 4 input pins for receiving 4 bits of the red, green and blue data from the data interfacing section over 18 times and 72 output pins for outputting the received red, green and blue data. Accordingly, each of the address electrode driving ICs processes the red, green and blue data corresponding to a multiple of 12. That is, the red, green and blue data arranged on an identical row of the interfacing section having the red, green and blue data arranged in 12 columns×107 rows are inputted in an identical address electrode driving IC. Accordingly, the data interfacing section can execute an operation for outputting the red, green and blue data although all of 1280 units of the red, green and blue data are not inputted.

Abstract: A flat panel display apparatus and a method for interfacing pixel data therein are disclosed.

Abstract: A method and an apparatus for variably controlling a switching timing of a power recovery circuit of a plasma display panel television is disclosed. A variableness range pulse generating section generates a variableness range pulse which determines a maximum variableness range of a recovered power applying time. A first counter counts a clock signal in response to the variableness range pulse and periodically outputs a counted value. Second and third counters count a switching time of first and second switches, respectively, and sets first and second reference values. A rising pulse generating section periodically compares the counted value with the first reference value and converts a logic level of an output signal from low to high when the counted value is identical with the first reference value. A falling pulse generating section periodically compares the counted value with the second reference value and converts a logic level of an output signal from high to low.

Abstract: A three electrodes face discharge color plasma display panel (PDP) is disclosed. The three electrodes face discharge color PDP comprises a front glass substrate, a back glass substrate, a plurality of partition walls, a plurality of scanning and sustaining electrode lines, a plurality of common sustaining electrode lines, and a plurality of address electrode lines. The plurality of scanning and sustaining electrode lines are formed on the front glass substrate. The common sustaining electrode lines and the adress electrode lines are formed on the back glass substrate. Therefore, the brightness of the whole picture can be enhanced as an intensity of a visible light passing the front substrate increases. Also, a discharge interference occuring between adjacent cells can be minimized as a discharge region of a discharge space is formed up and down.

Abstract: Disclosed is a timing circuit which produces control signals by which a data interfacing section can simultaneously implement input and output operations of a video data from a frame memory to an address electrode driving section, respectively. A first pulse signal whose pulse duration corresponds to a whole horizontal line time, a second pulse signal which is identical to a delayed first pulse signal by one horizontal line time and a third pulse signal whose pulse duration is one horizontal line time longer than that of the first pulse signal are produced by using a system clock signal of a 2 MHz frequency. During the pulse duration of the first and second pulse signals, first and second clock signals which contains 480 numbers of clock pulses with a period of one horizontal line time are produced by counting another system clock signal of a 25 MHz frequency.

Abstract: Disclosed is a timing circuit which produces control signals by which a data interfacing section can simultaneously implement input and output operations of a video data from a frame memory and to an address electrode driving section, respectively. A first pulse signal whose pulse duration corresponds to a whole horizontal line time, a second pulse signal which is identical to a delayed first pulse signal by one horizontal line time and a third pulse signal whose pulse duration is the one horizontal line time longer than that of the first pulse signal are produced by using a system clock signal of 2 MHz. During the pulse duration of the third pulse signal, a first clock signal which contains pulse signals whose numbers are one number larger than the numbers of whole horizontal lines (480) by using a system clock signal of 25 MHz. The first clock signal is provided to the data interfacing section to control the input and output operations thereof.

Abstract: An apparatus for L pixel data corresponding to 1 line input from a memory section to an upper and a lower address electrode driving sections, respectively in response to a control signal supplied from a timing control section. The data interfacing apparatus includes upper and lower data interfacing sections, and an input/output control section. The upper and the lower data interfacing sections includes a couple of temporality storing sections including a storing area for temporarily storing L/2 pixel data, an input selecting section for inputting 3N pixel data into the storing area over M (where M is a least integer which is greater than quotient of L divided by 3N) times in response to M input selecting control signals which are sequentially generated, and an output selecting section for outputting the L/2 pixel data stored in the storing area by P units over Q {=(L/2)/P} times in response to Q output selecting control signals which are sequentially generated, respectively.

Abstract: A data processing apparatus of an alternating current type plasma display panel system is disclosed. A plasma panel is divided into four subpanels by dividing vertically and horizontally, and 4 data interfacing sections take charge of driving the 4 subpanels, respectively. Numbers of upper and lower address electrodes are P. Each of the four data interfacing sections repeatedly receives N bits red-green-blue (RGB) data S times from a frame memory and, after storing a horizontal line RGB data, transfers D bits RGB data a time into 4 driving IC sections for driving address electrodes in a suitable order for data processing. Each of two driving IC sections for upper right and lower right subpanels takes charge of driving R address electrodes, and each of two driving IC sections for upper left and lower left subpanels takes charge of driving P-R address electrodes, where the number R can be decided by an equation, R=N.times.

Abstract: A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another.