Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: Provided are a method and apparatus for providing a network switching service to a user equipment.

Abstract: An example electronic device includes a display, a communication circuit, a memory, and at least one processor configured to, based on a signal for requesting transmission of identification information including a call word for using first mode of an artificial intelligence assistant function of the electronic device being received, from another electronic device, through the communication circuit using first communication method, control the display to display a user interface for requesting user confirmation for transmission of the identification information; control the communication circuit to transmit the identification information to the another electronic device as a result of user confirmation through the user interface; and receive information for using a second communication method from the another electronic device.

Abstract: Provided are a method and apparatus for a user equipment, a core network, and a second device to enable bidirectional communication for second devices. The method of the second device may include receiving internet protocol (IP) configuration information for automatically configuring an IP version 6 (IPv6) address of the second device from a core network through a user equipment; generating the IPv6 address using information in the IP configuration information; and transmitting the generated IPv6 address to the core network through the UE.

Abstract: Provided are a method and apparatus for providing a multi virtual local area network service to user equipments.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: An apparatus including a photovoltaic panel; a first fluid container thermally attached to a bottom of the photovoltaic panel; and a temperature sensor for sensing temperature of a fluid inside the first fluid container is part of a sub-system for a power generation system using solar energy. The sub-system further includes a heating assembly, including a second fluid container, a second temperature sensor, and an electrical heating element. The second fluid container is fluidically connected to the first fluid container. The heating element is configured to heat the pre-heated fluid in the second fluid container to its vapor state. The sub-system additionally includes a turbine generator fluidically connected to the second fluid container to generate AC power from the vapor. A system employing a plurality of sub-systems and a method for using the sub-systems are also provided.

Abstract: An apparatus including a photovoltaic panel; a first fluid container thermally attached to a bottom of the photovoltaic panel; and a temperature sensor for sensing temperature of a fluid inside the first fluid container is part of a sub-system for a power generation system using solar energy. The sub-system further includes a heating assembly, including a second fluid container, a second temperature sensor, and an electrical heating element. The second fluid container is fluidically connected to the first fluid container. The heating element is configured to heat the pre-heated fluid in the second fluid container to its vapor state. The sub-system additionally includes a turbine generator fluidically connected to the second fluid container to generate AC power from the vapor. A system employing a plurality of sub-systems and a method for using the sub-systems are also provided.

Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.

Abstract: Provided are a device and method for estimating carrier frequency offset of OFDM signals transmitted and received through a plurality of polarized antennas that may accurately estimate carrier frequency offset used for carrier frequency synchronization acquisition when there is interference between polarized waves.

Abstract: Provided are a device and method for estimating carrier frequency offset of OFDM signals transmitted and received through a plurality of polarized antennas that may accurately estimate carrier frequency offset used for carrier frequency synchronization acquisition when there is interference between polarized waves.

Abstract: A method for isolating Hepatitis A virus or Spring viremia of Carp virus. A virus probe is prepared by linking a magnetic bead-conjugated Protein G with an anti-HAV (Hepatitis A Virus) antibody or an anti-rhabdovirus antibody. The virus probe is contacted with a sample to be analyzed to form a virus probe-virus complex. The virus probe-virus complex is then isolated. It may specifically isolate Hepatitis A virus or Spring viremia of Carp virus from a sample mixed viruses.

Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

Abstract: A method for isolating Hepatitis A virus or Spring viremia of Carp virus. A virus probe is prepared by linking a magnetic bead-conjugated Protein G with an anti-HAV (Hepatitis A Virus) antibody or an anti-rhabdovirus antibody. The virus probe is contacted with a sample to be analyzed to form a virus probe-virus complex. The virus probe-virus complex is then isolated. It may specifically isolate Hepatitis A virus or Spring viremia of Carp virus from a sample mixed viruses.

Abstract: In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.

Abstract: A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a Si02 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 A or more. An interface trap density of the Si02 can be as high as lo?/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

Abstract: A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using inductively coupled plasma chemical vapor deposition (ICP-CVD). After the ICP-CVD, excimer laser annealing (ELA) is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiO2 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 ? or more. An interface trap density of the SiO2 can be as high as 1011/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

Abstract: In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.