Abstract: A memory device includes a memory array with a plurality of wordlines associated with memory cells of the memory array. Control logic is operatively coupled with the memory array. The control logic determines, in conjunction with a read operation directed at one or more strings of the memory cells, a number of wordlines that are associated with memory cells that have been programmed. The determining includes receiving, in a read command associated with a feature address of a selected wordline, a percentage value corresponding to the number of wordlines. The control logic adjusts, based on the number of wordlines, a read level voltage for the selected wordline of the one or more strings. The control logic causes, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

Abstract: A system includes a processing device, operatively coupled to a memory device, to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to a set of cache blocks of the memory device, the set of cache blocks including a first cache block and a second cache block, determining whether the first cache block is fully written and whether an amount of data written to the second cache block is greater than or equal to a threshold amount of data, and in response to determining that the first cache block is fully written and that the amount of data written to the second cache block is greater than or equal to the threshold amount of data, causing the data written to the set of cache blocks to be written to a target block of the memory device.

Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including identifying a set of cells of the memory array to be programmed with dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

Abstract: A memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. Page buffer(s) are coupled with the array(s). Logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. The logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. The logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.