Abstract: A microelectromechanical system (MEMS) device is provided that includes a substrate having a dielectric cavity formed therein and a movable electromechanical device suspended in the dielectric cavity. The dielectric cavity includes a substantially planar bottom surface and at least one sidewall surface extending substantially perpendicularly from the bottom surface. The movable electromechanical device is suspended in the dielectric cavity such that the movable electromechanical device is spaced apart from the bottom surface and the at least one sidewall surface of the dielectric cavity. The bottom surface of the cavity and each of the at least one sidewall surface of the cavity meet at a rectilinear corner.

Abstract: Suspended microelectromechanical systems (MEMS) devices including a stack of one or more materials over a cavity in a substrate are described. The suspended MEMS device may be formed by forming the stack, which may include one or more electrode layers and an active layer, over the substrate and removing part of the substrate underneath the stack to form the cavity. The resulting suspended MEMS device may include one or more channels that extend from a surface of the device to the cavity and the one or more channels have sidewalls with a spacer material. The cavity may have rounded corners and may extend beyond the one or more channels to form one or more undercut regions. The manner of fabrication may allow for forming the stack layers with a high degree of planarity.

Abstract: A microelectromechanical system (MEMS) device is provided that includes a substrate having a dielectric cavity formed therein and a movable electromechanical device suspended in the dielectric cavity. The dielectric cavity includes a substantially planar bottom surface and at least one sidewall surface extending substantially perpendicularly from the bottom surface. The movable electromechanical device is suspended in the dielectric cavity such that the movable electromechanical device is spaced apart from the bottom surface and the at least one sidewall surface of the dielectric cavity. The bottom surface of the cavity and each of the at least one sidewall surface of the cavity meet at a rectilinear corner.

Abstract: Suspended microelectromechanical systems (MEMS) devices including a stack of one or more materials over a cavity in a substrate are described. The suspended MEMS device may be formed by forming the stack, which may include one or more electrode layers and an active layer, over the substrate and removing part of the substrate underneath the stack to form the cavity. The resulting suspended MEMS device may include one or more channels that extend from a surface of the device to the cavity and the one or more channels have sidewalls with a spacer material. The cavity may have rounded corners and may extend beyond the one or more channels to form one or more undercut regions. The manner of fabrication may allow for forming the stack layers with a high degree of planarity.

Abstract: A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

Abstract: A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.

Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.

Abstract: A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.

Abstract: The present application addresses the problem arising during the erasure of EEPROMs where the FN tunnelling erase cycle is not self-limiting. Existing methods address this problem by employing monitoring algorithms. However, these algorithms slow the erase procedure time. The present application provides an alternative method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The method comprises the initial step of raising the potential at the erase gate and lowering the potential at the control gate to cause FN tunnelling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a sufficient value to cause to start FN tunnelling through the oxide of the transistor. A new structure particularly suitable for this method is also disclosed.

Abstract: A method for forming an LDNMOS (1) and LDPMOS (2) in a CMOS process comprises forming the LDNMOS (1) and LDPMOS (2) to a stage where a gate (14) is laid down on a gate oxide layer (12) and a locos (9) is formed over the respective N and P-wells (4) and (5) of the LDNMOS (1) and LDPMOS (2). A P-body (15) is formed in the N-well (4) of the LDNMOS (1) by implanting a boron dopant in two stages, in the first stage at a first tilt angle (&thgr;) of 45° for forming the P-body (15) beneath the gate (14) for determining the source/drain threshold voltage, and subsequently at a second tilt angle (&phgr;) of 7° for extending the P-body (15) downwardly at (25) for determining the punchthrough breakdown voltage of the LDNMOS (1). The formation of an N-body (16) in a P-well (5) of the LDPMOS (2) is similar to the formation of the P-body (15) with the exception that the dopant is a phosphorous dopant.