Abstract: A system and method are provided for framing messages in a forward error correction (FEC) structure for data streams encoded with redundant signal conditioning information. The method accepts signal conditioning-encoded words at a first bit rate, and eliminates redundant information in the signal conditioning-encoded words, creating N reduced-bit words of k bits. The k-bit words are mapped into a payload field of N*(k/p) p-bit words. Overhead (OH) and FEC parity fields are generated, and a frame is created including the OH field, payload field, and FEC parity field. The bit values in the frame are then pseudorandomly scrambled and the scrambled frame is transmitted at the first bit rate. A system and method are also presented for recovering the signal conditioning-encoded words from an FEC frame.

Abstract: A system and method are provided for using disparity measurements to control the adjustment of a data slicer threshold. The method receives a serial stream of pseudorandom digital data signals having an average DC value, and compares data signal amplitudes to a slicer threshold value. In response to the slicer threshold value comparison, data signal “1” and “0” values are determined. A first sum of determined “1” values is created, and a second sum of determined “0” values is created. The slicer threshold value is adjusted in response to the comparison of the first and second sums. More explicitly, the slicer threshold value is adjusted to make “1” values more likely in response to the second sum being larger than the first sum. Alternately, the slicer threshold value is adjusted to make “0” values more likely in response to the second sum being smaller than the first sum.

Abstract: A system and method are provided for using disparity measurements to control the adjustment of a data slicer threshold. The method receives a serial stream of pseudorandom digital data signals having an average DC value, and compares data signal amplitudes to a slicer threshold value. In response to the slicer threshold value comparison, data signal “1” and “0” values are determined. A first sum of determined “1” values is created, and a second sum of determined “0” values is created. The slicer threshold value is adjusted in response to the comparison of the first and second sums. More explicitly, the slicer threshold value is adjusted to make “1” values more likely in response to the second sum being larger than the first sum. Alternately, the slicer threshold value is adjusted to make “0 ” values more likely in response to the second sum being smaller than the first sum.

Abstract: A system and method are provided for framing messages in a forward error correction (FEC) structure for data streams encoded with redundant signal conditioning information. The method accepts signal conditioning-encoded words at a first bit rate, and eliminates redundant information in the signal conditioning-encoded words, creating N reduced-bit words of k bits. The k-bit words are mapped into a payload field of N*(k/p) p-bit words. Overhead (OH) and FEC parity fields are generated, and a frame is created including the OH field, payload field, and FEC parity field. The bit values in the frame are then pseudorandomly scrambled and the scrambled frame is transmitted at the first bit rate. A system and method are also presented for recovering the signal conditioning-encoded words from an FEC frame.

Abstract: A digital communications system that can asynchronously map/de-map digital signals from one clock domain to another, while reducing mapping jitter levels and permitting higher levels of integration. The digital communications system includes an asynchronous stuff bit insertion circuit, an asynchronous stuff bit removal circuit, and a communications network connected therebetween. The asynchronous stuff bit insertion circuit includes a first elastic store, a barrel shifter, and a stuffing circuit. The asynchronous stuff bit removal circuit includes a de-stuffing circuit, a second elastic store, and a frequency control path including a phase-locked loop having a variable divider circuit, the operation of which is controlled based on the presence/absence of stuff bits in the data provided to the de-stuffing circuit.

Abstract: A digital communications system that can asynchronously map/de-map digital signals from one clock domain to another, while reducing mapping jitter levels and permitting higher levels of integration. The digital communications system includes an asynchronous stuff bit insertion circuit, an asynchronous stuff bit removal circuit, and a communications network connected therebetween. The asynchronous stuff bit insertion circuit includes a first elastic store, a barrel shifter, and a stuffing circuit. The asynchronous stuff bit removal circuit includes a de-stuffing circuit, a second elastic store, and a frequency control path including a phase-locked loop having a variable divider circuit, the operation of which is controlled based on the presence/absence of stuff bits in the data provided to the de-stuffing circuit.