Patents by Inventor Sean Casey

Sean Casey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180233834
    Abstract: A leaf spring compression system comprising a mechanical assembly for securing a plurality of leaf springs on a battery cell stack of a flow battery system is disclosed. The cell stack may, comprise: a plurality of cells stacked together to form a flow battery; and a compression system comprising at least two tie rods extending through the plurality of cells clamping a spring acting at opposite ends to compress the cells together, the spring contacting at least two fulcrum elements positioned between the tie rods. In this way, the compression system may exert uniform loading on the battery cell stack, while minimizing deflection of pressure plates attached to the cell stack.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 16, 2018
    Inventors: Craig E. Evans, Sean Casey
  • Publication number: 20170256803
    Abstract: A redox flow battery may include: a membrane interposed between a first electrode positioned at a first side of the membrane and a second electrode positioned at a second side of the membrane opposite to the first side; a first flow field plate comprising a plurality of positive flow field ribs, each of the plurality of positive flow field ribs contacting the first electrode at first supporting regions on the first side; and the second electrode, including an electrode spacer positioned between the membrane and a second flow field plate, the electrode spacer comprising a plurality of main ribs, each of the plurality of main ribs contacting the second flow field plate at second supporting regions on the second side, each of the second supporting regions aligned opposite to one of the plurality of first supporting regions. As such, a current density distribution at a plating surface may be reduced.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Craig E. Evans, Sean Casey, Yang Song
  • Patent number: 9534457
    Abstract: An apparatus for use in connection using a drill having a drilling element for forming a borehole in a face of a mine passage includes a drill guide for engaging the drilling element while permitting the drilling element to move toward the face for forming the borehole. The drill guide includes a keeper for keeping the drilling element in a desired position, which keeper is biased for pivoting movement upon the application of a manual force between an active position for capturing the drilling element and a retracted position for releasing the drilling element. A low profile drill guide is also disclosed, as is a guard for a drill guide, and also related methods.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: January 3, 2017
    Assignee: J.H. FLETCHER & CO
    Inventors: Henry E. Wilson, Sean Casey Farrell, Robert Sherwood Anderson, Sean Joseph McQuerrey
  • Publication number: 20140231137
    Abstract: An apparatus for use in connection using a drill having a drilling element for forming a borehole in a face of a mine passage includes a drill guide for engaging the drilling element while permitting the drilling element to move toward the face for forming the borehole. The drill guide includes a keeper for keeping the drilling element in a desired position, which keeper is biased for pivoting movement upon the application of a manual force between an active position for capturing the drilling element and a retracted position for releasing the drilling element. A low profile drill guide is also disclosed, as is a guard for a drill guide, and also related methods.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 21, 2014
    Applicant: J.H. FLETCHER & CO
    Inventors: Henry E. WILSON, Sean Casey FARRELL, Robert Sherwood ANDERSON, Sean Joseph MCQUERREY
  • Patent number: 7176846
    Abstract: A passive integrated transponder (PIT) tag comprising an integrated circuit and a unitary core is described. The unitary core comprises a coil-forming portion proximate one end thereof and an integrated circuit support portion proximate an opposite end thereof. The integrated circuit support portion extends beneath and supports the integrated circuit.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: February 13, 2007
    Assignee: Digital Angel Corporation
    Inventors: Ezequiel Mejia, Sean Casey
  • Publication number: 20050253983
    Abstract: The invention provides materials and methods for making anisotropic solids which may be in the form of films, layers, shaped elements, and other shaped articles. The methods provide anisotropic solids without the need for rolling, rubbing, or stretching to impart orientational alignment of the molecules of the solid. The methods employ organic or organometallic compounds which are soluble orienting molecules. The solvent or solvent system must be sufficiently volatile to be removed without disruption of the molecular orientation. The soluble orienting molecules include those containing one or more hydrophilic and/or ionic groups and the solvent or solvent system can be a polar organic solvent or solvent system or an aqueous solvent or solvent system. The invention also provides novel compounds having quaterrylene, perylene and naphthalene ring systems carrying one or more hydrophilic and/or ionic groups.
    Type: Application
    Filed: November 22, 2004
    Publication date: November 17, 2005
    Inventors: Travis Carson, Sean Casey, Isaac Iverson, Wonewoo Seo, Suk-Wah Tam-Chang
  • Publication number: 20050256393
    Abstract: A method of generating three-dimensional T1 and T2 maps for steady state imaging involves acquiring a first set of spoiled gradient echo images with contrast dependent on T1. A second set of fully refocused gradient echo images with contrast dependent upon T1 and T2 is then acquired. A T1 map is generated from the first set of images and a T2 map is generated from the second set of fully refocused gradient echo images and the T1 map.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 17, 2005
    Inventors: Sean Casey Louis Deoni, Brian Rutt, Terence Peters
  • Publication number: 20050248460
    Abstract: A passive integrated transponder (PIT) tag comprising an integrated circuit and a unitary core is described. The unitary core comprises a coil-forming portion proximate one end thereof and an integrated circuit support portion proximate an opposite end thereof. The integrated circuit support portion extends beneath and supports the integrated circuit.
    Type: Application
    Filed: July 13, 2005
    Publication date: November 10, 2005
    Inventors: Ezequiel Mejia, Sean Casey
  • Patent number: 6947004
    Abstract: A passive integrated transponder (PIT) tag comprising an integrated circuit and a unitary core is described. The unitary core comprises a coil-forming portion proximate one end thereof and an integrated circuit support portion proximate an opposite end thereof. The integrated circuit support portion extends beneath and supports the integrated circuit.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: September 20, 2005
    Assignee: Digital Angel Corporation
    Inventors: Ezequiel Mejia, Sean Casey
  • Publication number: 20050144697
    Abstract: The present invention comprises an improved camouflage system to be used for clothing generally employed by hunters, photographers and the like for the purpose of visual concealment in natural environments. An open, interlaced fabric substrate is employed as part of a garment to be worn by the user. A plurality of preconfigured camouflage elements are coupled to the fabric substrate. Each camouflage element comprises an elongated central mesh element, each end thereof depending into panels having multiple lobes to simulate leaves or other natural flora. The camouflage elements are dyed or otherwise colored with contrasting indicia in a manner consistent with a selected natural environment.
    Type: Application
    Filed: January 2, 2004
    Publication date: July 7, 2005
    Inventor: Sean Casey
  • Publication number: 20030107648
    Abstract: A surveillance system includes video surveillance cameras that are in various locations sought to be monitored. Each camera is associated with a variable frame rate that is faster when motion is detected in the location and slower when little or no motion is detected, to improve resolution when needed. A system hub receives video feeds from the cameras and sends them on to wireless clients upon client request.
    Type: Application
    Filed: December 12, 2001
    Publication date: June 12, 2003
    Inventors: Richard Stewart, Keith Trahan, David Chesavage, Sean Casey, Michael Rome, Chris Kokinakes
  • Publication number: 20020154065
    Abstract: A passive integrated transponder (PIT) tag comprising an integrated circuit and a unitary core is described. The unitary core comprises a coil-forming portion proximate one end thereof and an integrated circuit support portion proximate an opposite end thereof. The integrated circuit support portion extends beneath and supports the integrated circuit.
    Type: Application
    Filed: February 4, 2002
    Publication date: October 24, 2002
    Inventors: Ezequiel Mejia, Sean Casey
  • Patent number: 6400338
    Abstract: A passive integrated transponder (PIT) tag comprising an integrated circuit and a unitary core is described. The unitary core comprises a coil-forming portion proximate one end thereof and an integrated circuit support portion proximate an opposite end thereof. The integrated circuit support portion extends beneath and supports the integrated circuit.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: June 4, 2002
    Assignee: Destron-Fearing Corporation
    Inventors: Ezequiel Mejia, Sean Casey
  • Patent number: 6080022
    Abstract: A connection system for providing a consumer-friendly connection between an expansion card and a host device. The host device includes a male connection while the expansion card includes a female connection. The male and female connections are arranged in a pattern that allows a combination of keyed voltage connections between the host device and expansion card when the supply voltage of the host and operating voltage of the card are compatible. The male connection includes six different supply voltage combinations that include a first voltage only, a second voltage only, a third voltage only, a first and second voltage only, a second and third voltage only, and a first, second and third voltage combination. In addition, the female connection includes six different expansion card operating voltage combinations that include a first voltage only, a second voltage only, a third voltage only, a first and second voltage only, a second and third voltage only, and a first, second and third voltage combination.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: June 27, 2000
    Assignee: Intel Corporation
    Inventors: Anthony J. Shaberman, Michael Sean Casey
  • Patent number: 6055593
    Abstract: The miniature card uses an Attribute Information Structure (AIS) for card recognition. The PC Card specification uses a Card Information Structure (CIS) for card recognition. The dual information structure definition provides a mechanism to allow a miniature card to be recognized and functional in both a PC Card environment and miniature card environment. The dual information structure mechanism incorporates the AIS structure into the CIS structure within the miniature card, thus allowing a card to be recognized and function in both environments.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: April 25, 2000
    Assignee: Intel Corporation
    Inventors: Tony Shaberman, Thomas Newman, Sean Casey
  • Patent number: 6011486
    Abstract: An electronic paging device has a port including a plurality of conductors to connect to a computer system, and interface logic to assert and receive signals on the plurality of conductors to transfer data to and from the computer system.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: January 4, 2000
    Assignee: Intel Corporation
    Inventor: M. Sean Casey
  • Patent number: 5761732
    Abstract: A method and apparatus for interfacing a memory card with a system having a smaller bus width while maintaining its interchangeability with other systems having larger bus widths. The host accesses data stored in the memory card using an interleaving scheme, such as a two-way interleaving scheme. The host provides a first enable signal and a second enable signal. In response to the first enable signal, data is accessed from a first section of the addressed memory location, and in response to the second enable signal, data is accessed from a second section of the addressed memory location. The first section of the addressed memory location may store even data bytes and the second section of the addressed memory location may store odd data bytes. The host may only access one section of the selected memory location at a time when using the interleaving scheme.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: June 2, 1998
    Assignee: Intel Corporation
    Inventors: Tony Shaberman, Sean Casey