Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing electro-magnetic fields to at least partially cancel resulting in a reduction in interference between the inductors. The polarities of the magnetic fields produced by each inductor are opposite to each other so that at least a partial cancellation results when the fields interfere with each other.

Abstract: A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing electro-magnetic fields to at least partially cancel resulting in a reduction in interference between the inductors. The polarities of the magnetic fields produced by each inductor are opposite to each other so that at least a partial cancellation results when the fields interfere with each other.

Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains a first and second contact region. These contact regions extend downward from the surface of the substrate. A third contact is located within the diffusion region between the first and second contacts. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor. The third contact forms a Schottky diode such that application of a voltage to this contact forms a depletion region within the diffusion region. The depletion region changes in size depending on the voltage applied to the third contact to change the resistance of the depletion resistor.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p? diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.

Abstract: An improved semiconductor capacitor and a method for fabricating the capacitor. The capacitor is located on a substrate having a first conductive section with a first outer plate connected to a first inner plate. A second conductive section having a second outer plate connected to a second inner plate is present in the capacitor. The second inner plate is located within a first hole in the first outer plate and the first inner plate is located within a second hole in the second outer plate such that a first distance is present between the second inner plate and the first outer plate and a second distance is present between the first inner plate and the second outer plate. Multiple layers of sections like the first conductive section and the second conductive section are stacked over each other and are connected to each other as part of the capacitor. Via connections may be used to connect the layers.