Abstract: An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask.

Abstract: A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line.

Abstract: A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line.

Abstract: A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line.

Abstract: A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line.

Abstract: Disclosed is a topcoat composition comprising a polymer having a dissolution rate of at least 1500 ?/second in an aqueous alkaline developer, and at least one solvent. The topcoat composition can be used to coat a photoresist layer on a material layer on a substrate, for example, a semiconductor chip. Also disclosed is a method of forming a pattern in the material layer of the coated substrate.

Abstract: A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer.