Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surface areas in different planes, such as horizontal and vertical, are provided between said first and second plates. The plate to plate capacitor can be formed as a stack of layers in which one or more alternating first and third insulating layers each have first and second conductive lines configured therein and in which one or more second insulating layers having conductive vias formed therein interpose respective first and third insulating layers. The first and second conductive lines in the first insulating layer(s) are interconnected by the conductive vias to the first and second conductive lines, respectively, in the third layer(s) so as to interlace the first and second metal conductive lines together.

Abstract: A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surface areas in different planes, such as horizontal and vertical, are provided between said first and second plates. The plate to plate capacitor can be formed as a stack of layers in which one or more alternating first and third insulating layers each have first and second conductive lines configured therein and in which one or more second insulating layers having conductive vias formed therein interpose respective first and third insulating layers. The first and second conductive lines in the first insulating layer(s) are interconnected by the conductive vias to the first and second conductive lines, respectively, in the third layer(s) so as to interlace the first and second metal conductive lines together.

Abstract: A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that the tunable resistor is a p-type polysilicon resistor means that this structure can easily be integrated into the process since polysilicon is used as a gate material for basic CMOS processing.

Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.

Abstract: A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that the tunable resistor is a p-type polysilicon resistor means that this structure can easily be integrated into the process since polysilicon is used as a gate material for basic CMOS processing.

Abstract: Techniques are provided for localized use of high-K dielectric material within a capacitor structure. Low-K dielectric is deposited or spun on as usual. Then, a larger area is etched back and then filled with high-K dielectric material. The high-K dielectric material is then patterned and copper routing lines are trenched in and then filled with metal. A dual damascene process may be used to connect a second metal layer using a series of vias for each metal line. In an aluminum process, an insulator layer is formed over the substrate and an aluminum layer is formed over the insulator layer. The aluminum layer is etched back to for metal lines over the insulator layer. The remaining area is filled with low-K dielectric. Then, the area between the metal lines is etched back and filled with high-K dielectric to increase the capacitance value of the structure.

Abstract: A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p? diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.

Abstract: A voltage-controlled, variable polysilicon resistor is formed of polysilicon deposited in the first interlayer dielectric layer at the same time that polysilicon routing is created. The polysilicon resistor, which is formed of n? doped polysilicon, has three contact regions connected to the metal layers. A region at either end of the resistor is doped n+ and forms the positive and negative terminals of the resistor. A third contact region is located within the polysilicon region between the first and second contacts to form a Schottky diode such that application of a voltage to this contact forms a depletion region within the polysilicon region. The depletion region changes in size depending on the voltage applied to the third contact to change the resistance of the depletion resistor.

Abstract: An improved semiconductor capacitor and a method for fabricating the capacitor. The capacitor is located on a substrate having a first conductive section with a first outer plate connected to a first inner plate. A second conductive section having a second outer plate connected to a second inner plate is present in the capacitor. The second inner plate is located within a first hole in the first outer plate and the first inner plate is located within a second hole in the second outer plate such that a first distance is present between the second inner plate and the first outer plate and a second distance is present between the first inner plate and the second outer plate. Multiple layers of sections like the first conductive section and the second conductive section are stacked over each other and are connected to each other as part of the capacitor. Via connections may be used to connect the layers.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains a first and second contact region. These contact regions extend downward from the surface of the substrate. A third contact is located within the diffusion region between the first and second contacts. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor. The third contact forms a Schottky diode such that application of a voltage to this contact forms a depletion region within the diffusion region. The depletion region changes in size depending on the voltage applied to the third contact to change the resistance of the depletion resistor.

Abstract: A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.