Abstract: A system and method for generating a synthetic clock signal in synchronism with both a high frequency clock signal and low frequency clock signal, where the rising and falling edges of the low frequency clock signal are subject to material skew. The frequency ratio between the high and low frequency clock signals is derived by sampling the low frequency clock signal at the frequency of the high frequency cloak signal. The synthesized low frequency clock signal is generated directly from the high frequency clock signal using the determined relative frequency ratio. The synthetic clock signal is also in synchronism with the low frequency clock signal. Since the synthetic clock signal is derived directly from the high frequency clock signal, it is not subject to the skew problems of the low frequency clock signal.

Abstract: A bus interface with resources to selectively optimize burst mode data transfers from one bus to another through an automated selection and generation of a cadence. In one form, the cadence is selected based upon memory access latency characteristics, the relative widths of the busses, and the relative clock frequencies of the busses. The selected cadence is provided as a pacing ready signal to the bus receiving the transferred data.