Patents by Inventor Sean Hearne

Sean Hearne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7834422
    Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallized to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: November 16, 2010
    Assignee: Qucor Pty. Ltd.
    Inventors: Soren Andresen, Andrew Steven Dzurak, Eric Gauja, Sean Hearne, Toby Felix Hopf, David Norman Jamieson, Mladen Mitic, Steven Prawer, Changyi Yang
  • Publication number: 20070252240
    Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallised to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.
    Type: Application
    Filed: May 18, 2005
    Publication date: November 1, 2007
    Applicant: QUCOR PTY LTD
    Inventors: Soren Andresen, Andrew Dzurak, Eric Gauja, Sean Hearne, Toby Hopf, David Jamieson, Mladen Mitic, Steven Prawer, Changyi Yang
  • Publication number: 20050272253
    Abstract: An electroplated metal alloy including at least three elements. A multilayer interconnection structure that includes a substrate that is an interior of the interconnection structure, a conductive seed layer exterior to the substrate, and an electroplated metal alloy layer including at least three elements exterior to the conductive seed layer. A multilayer interconnection structure formed on a substrate, that includes a barrier layer, and a conductive seed layer, wherein the improvement includes an electroplated metal alloy layer including at least three elements. A method for forming a multilayer interconnection structure that includes providing a substrate, depositing a conductive seed layer, and electroplating a metal alloy layer including at least three elements exterior to the conductive seed layer.
    Type: Application
    Filed: July 8, 2005
    Publication date: December 8, 2005
    Inventors: Grant Kloster, Sean Hearne
  • Publication number: 20030194857
    Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, wherein the conductive layer includes a sufficient amount of a dopant, which will diffuse in the direction that is opposite to the direction in which electrons will flow through the conductive layer, to reduce the electromigration of the material that comprises the bulk of the conductive layer without significantly increasing the conductive layer's resistance.
    Type: Application
    Filed: April 11, 2002
    Publication date: October 16, 2003
    Inventors: Stefan Hau-Riege, Christine Hau-Riege, Jihperng Leu, Kevin Fischer, Pei-Hua Wang, Sean Hearne