Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.

Abstract: Resizing circuitry comprises at least one buffer having buffer entries each corresponding to one of at least two shift registers, each shift register comprising storage circuits connected in a ring to transfer a token bit between storage circuits. Selection circuitry controls, based on the shift registers, writing of data sections of input data units having a first number of data sections to the buffer(s), to form output data units having a second number of data sections. For a given buffer entry corresponding to a given shift register, depending on whether the token bit is stored in a first or second subset of storage circuits, the selection circuitry controls writing of a selected data section of a received input data unit to the given buffer entry or prevents overwriting of the given buffer entry. At least two of the shift registers have different relative arrangements of the first and second subsets of storage circuits.

Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

Abstract: An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location.

Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second r

Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.

Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second r

Abstract: An interconnect, and method of handling supplementary data in an interconnect, are provided. The interconnect has routing circuitry providing a plurality of paths, and routing control circuitry to use the plurality of paths to establish routes through the interconnect between source devices and destination devices coupled to the interconnect, to enable system data to be routed through the interconnect between the source devices and the destination devices. The system data relates to functional operation of a system comprising the interconnect, the source devices and the destination devices. At least a subset of the paths are redundant paths whose use by the routing control circuitry provides the system data with resilience to faults when routing the system data through the interconnect.

Abstract: An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location.

Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

Abstract: An interconnect, and method of handling supplementary data in an interconnect, are provided. The interconnect has routing circuitry providing a plurality of paths, and routing control circuitry to use the plurality of paths to establish routes through the interconnect between source devices and destination devices coupled to the interconnect, to enable system data to be routed through the interconnect between the source devices and the destination devices. The system data relates to functional operation of a system comprising the interconnect, the source devices and the destination devices. At least a subset of the paths are redundant paths whose use by the routing control circuitry provides the system data with resilience to faults when routing the system data through the interconnect.

Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.

Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.

Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.