Abstract: A method of transceiving data includes providing a wireless transceiver chip that supports multiple wireless standards for transceiving data packets, wherein a first wireless standard comprises a first modulation and demodulation scheme, and wherein a second wireless standard comprises a second modulation and demodulation scheme, and wherein the first modulation and demodulation scheme is incompatible with the second modulation and demodulation scheme; activating only one PHY layer of the wireless transceiver chip during the transceiving of the data packets; using a MAC layer of the wireless transceiver chip to specify whether the first or second wireless standard is to be used for a given transceiving of the data packets; and the PHY layer receiving instructions from the MAC layer regarding which wireless standard is to be used for the transceiving of the data packets using hardware that is shared by the PHY layer corresponding to both wireless standards.

Abstract: A method of transceiving data includes providing a wireless transceiver chip that supports multiple wireless standards for transceiving data packets, wherein a first wireless standard comprises a first modulation and demodulation scheme, and wherein a second wireless standard comprises a second modulation and demodulation scheme, and wherein the first modulation and demodulation scheme is incompatible with the second modulation and demodulation scheme; activating only one PHY layer of the wireless transceiver chip during the transceiving of the data packets; using a MAC layer of the wireless transceiver chip to specify whether the first or second wireless standard is to be used for a given transceiving of the data packets; and the PHY layer receiving instructions from the MAC layer regarding which wireless standard is to be used for the transceiving of the data packets using hardware that is shared by the PHY layer corresponding to both wireless standards.

Abstract: A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic is described. The circuit comprises a block of memory cells comprising a look-up table of a configurable logic block; and a reset signal coupled to the block of memory elements, the reset signal enabling partial reconfiguration of the memory cells of the configurable logic block. Each the memory cell may be coupled to receive the reset signal enabling the partial reconfiguration of the block of memory cells of the configurable logic block. The reset signal may comprise a plurality of signals, wherein each signal of the plurality of signals is coupled to a memory cell of the block of memory cells. Each memory cell may also receive a signal for setting an initial state. A method of enabling partial reconfiguration of memory cells of a look-up table of a programmable logic device is also described.