Patents by Inventor Sean L. Manion

Sean L. Manion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    Publication number: 20240020033
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Application
    Filed: September 11, 2023
    Publication date: January 18, 2024
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • Sequential data optimized sub-regions in storage devices
    Patent number: 11755214
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 12, 2023
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    Publication number: 20220214821
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Chistian M. Gyllenskog, Kulachet Tanpairoj
  • Sequential data optimized sub-regions in storage devices
    Patent number: 11294585
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    Publication number: 20210109666
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • Sequential data optimized sub-regions in storage devices
    Patent number: 10871907
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    Publication number: 20200210080
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj